From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.4 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65D9AC433E0 for ; Tue, 2 Jun 2020 23:30:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 45E292072F for ; Tue, 2 Jun 2020 23:30:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="JtxlATgt" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728390AbgFBXaX (ORCPT ); Tue, 2 Jun 2020 19:30:23 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:46648 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726809AbgFBXaX (ORCPT ); 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Tue, 2 Jun 2020 18:18:10 -0500 Received: from [10.250.52.63] (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 052NI9Kh009536; Tue, 2 Jun 2020 18:18:09 -0500 Subject: Re: [PATCH net-next v5 4/4] net: dp83869: Add RGMII internal delay configuration To: Florian Fainelli , , , , CC: , , References: <20200602164522.3276-1-dmurphy@ti.com> <20200602164522.3276-5-dmurphy@ti.com> <61888788-041f-7b93-9d99-7dad4c148021@ti.com> <6981527b-f155-a46b-574a-2e6621589ca4@gmail.com> From: Dan Murphy Message-ID: Date: Tue, 2 Jun 2020 18:18:04 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: <6981527b-f155-a46b-574a-2e6621589ca4@gmail.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Florian On 6/2/20 6:13 PM, Florian Fainelli wrote: > > On 6/2/2020 4:10 PM, Dan Murphy wrote: >> Florian >> >> On 6/2/20 5:33 PM, Florian Fainelli wrote: >>> On 6/2/2020 9:45 AM, Dan Murphy wrote: >>>> Add RGMII internal delay configuration for Rx and Tx. >>>> >>>> Signed-off-by: Dan Murphy >>>> --- >>> [snip] >>> >>>> + >>>>   enum { >>>>       DP83869_PORT_MIRRORING_KEEP, >>>>       DP83869_PORT_MIRRORING_EN, >>>> @@ -108,6 +113,8 @@ enum { >>>>   struct dp83869_private { >>>>       int tx_fifo_depth; >>>>       int rx_fifo_depth; >>>> +    s32 rx_id_delay; >>>> +    s32 tx_id_delay; >>>>       int io_impedance; >>>>       int port_mirroring; >>>>       bool rxctrl_strap_quirk; >>>> @@ -232,6 +239,22 @@ static int dp83869_of_init(struct phy_device >>>> *phydev) >>>>                    &dp83869->tx_fifo_depth)) >>>>           dp83869->tx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB; >>>>   +    ret = of_property_read_u32(of_node, "rx-internal-delay-ps", >>>> +                   &dp83869->rx_id_delay); >>>> +    if (ret) { >>>> +        dp83869->rx_id_delay = >>>> +                dp83869_internal_delay[DP83869_CLK_DELAY_DEF]; >>>> +        ret = 0; >>>> +    } >>>> + >>>> +    ret = of_property_read_u32(of_node, "tx-internal-delay-ps", >>>> +                   &dp83869->tx_id_delay); >>>> +    if (ret) { >>>> +        dp83869->tx_id_delay = >>>> +                dp83869_internal_delay[DP83869_CLK_DELAY_DEF]; >>>> +        ret = 0; >>>> +    } >>> It is still not clear to me why is not the parsing being done by the PHY >>> library helper directly? >> Why would we do that for these properties and not any other? > Those properties have a standard name, which makes them suitable for > parsing by the core PHY library. >> Unless there is a new precedence being set here by having the PHY >> framework do all the dt node parsing for common properties. > You could parse the vendor properties through the driver, let the PHY > library parse the standard properties, and resolve any ordering > precedence within the driver. In general, I would favor standard > properties over vendor properties. > > Does this help? Ok so new precedence then. Because there are common properties like tx-fifo-depth, rx-fifo-depth, enet-phy-lane-swap and max_speed that the PHY framework should parse as well. Dan