From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.3 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E021C4BA1D for ; Wed, 26 Feb 2020 17:12:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 81C3424685 for ; Wed, 26 Feb 2020 17:12:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726538AbgBZRMj (ORCPT ); Wed, 26 Feb 2020 12:12:39 -0500 Received: from foss.arm.com ([217.140.110.172]:39386 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726063AbgBZRMi (ORCPT ); Wed, 26 Feb 2020 12:12:38 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5061330E; Wed, 26 Feb 2020 09:12:38 -0800 (PST) Received: from [10.1.196.105] (eglon.cambridge.arm.com [10.1.196.105]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 218623F881; Wed, 26 Feb 2020 09:12:34 -0800 (PST) Subject: Re: [PATCH 1/2] dt-bindings: edac: Add DT bindings for Kryo EDAC To: Sai Prakash Ranjan Cc: Andy Gross , Bjorn Andersson , Mark Rutland , Rob Herring , devicetree@vger.kernel.org, Borislav Petkov , Mauro Carvalho Chehab , Tony Luck , Robert Richter , linux-edac@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Stephen Boyd , Evan Green , tsoni@codeaurora.org, psodagud@codeaurora.org, baicar@os.amperecomputing.com References: <0101016ed57a3259-eee09e9e-e99a-40f1-ab1c-63e58a42615c-000000@us-west-2.amazonses.com> <312fc8b8-7019-0c74-6a92-c6740cab5dad@arm.com> <3c3b1d8107a26bbbf8daca3a6c43caca@codeaurora.org> From: James Morse Message-ID: Date: Wed, 26 Feb 2020 17:12:30 +0000 User-Agent: Mozilla/5.0 (X11; Linux aarch64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <3c3b1d8107a26bbbf8daca3a6c43caca@codeaurora.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-GB Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Sai, On 24/01/2020 14:21, Sai Prakash Ranjan wrote: > On 2020-01-16 00:18, James Morse wrote: >> On 05/12/2019 09:53, Sai Prakash Ranjan wrote: >>> This adds DT bindings for Kryo EDAC implemented with RAS >>> extensions on KRYO{3,4}XX CPU cores for reporting of cache >>> errors. >>> diff --git a/Documentation/devicetree/bindings/edac/qcom-kryo-edac.yaml >>> b/Documentation/devicetree/bindings/edac/qcom-kryo-edac.yaml >>> new file mode 100644 >>> index 000000000000..1a39429a73b4 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/edac/qcom-kryo-edac.yaml >> There is also an MMIO interface which needs a base address, along with >> the index and >> ranges. (which may be different). The same component may use both the >> system register and the MMIO interface. > I have some doubts here, Where do I get this info? Will this be implementation specific? It will be implementation specific. The ACPI spec folk have gathered some of the range of ways people are putting this together. We should take that into account with the binding, otherwise we end up with a 'v1' and 'v2' of the binding and have to support both. There is a 'Beta 2' of that ACPI document. It should appear on the website at some point. Qualcomm should have this somewhere, its called 'DEN0085_RAS_ACPI_1.0_RELEASE_BETA2.pdf. Thanks, James