From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94EB6C07E95 for ; Tue, 13 Jul 2021 16:48:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 69D30611AC for ; Tue, 13 Jul 2021 16:48:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231406AbhGMQuy (ORCPT ); Tue, 13 Jul 2021 12:50:54 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:51546 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S229604AbhGMQux (ORCPT ); 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Tue, 13 Jul 2021 18:47:48 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 56DD610002A; Tue, 13 Jul 2021 18:47:45 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag2node3.st.com [10.75.127.6]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 3E89F248ED3; Tue, 13 Jul 2021 18:47:45 +0200 (CEST) Received: from lmecxl0993.lme.st.com (10.75.127.44) by SFHDAG2NODE3.st.com (10.75.127.6) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 13 Jul 2021 18:47:44 +0200 Subject: Re: [PATCH] drm/stm: dsi: compute the transition time from LP to HS and back To: Antonio Borneo , Yannick Fertre , Benjamin Gaignard , David Airlie , Daniel Vetter , Maxime Coquelin , Alexandre Torgue , Raphael Gallais-Pou , , , CC: References: <20210713144941.3599-1-antonio.borneo@foss.st.com> From: Philippe CORNU Message-ID: Date: Tue, 13 Jul 2021 18:47:44 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210713144941.3599-1-antonio.borneo@foss.st.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.75.127.44] X-ClientProxiedBy: SFHDAG1NODE3.st.com (10.75.127.3) To SFHDAG2NODE3.st.com (10.75.127.6) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391,18.0.790 definitions=2021-07-13_10:2021-07-13,2021-07-13 signatures=0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Antonio, On 7/13/21 4:49 PM, Antonio Borneo wrote: > The driver uses a conservative set of hardcoded values for the > maximum time delay of the transitions between LP and HS, either > for data and clock lanes. > > By using the info in STM32MP157 datasheet, valid also for other ST > devices, compute the actual delay from the lane's bps. > > Signed-off-by: Antonio Borneo > --- > To: Yannick Fertre > To: Philippe Cornu > To: Benjamin Gaignard > To: David Airlie > To: Daniel Vetter > To: Maxime Coquelin > To: Alexandre Torgue > To: Raphael Gallais-Pou > To: dri-devel@lists.freedesktop.org > To: linux-stm32@st-md-mailman.stormreply.com > To: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > > drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 17 +++++++++++++---- > 1 file changed, 13 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c > index 8399d337589d..32cb41b2202f 100644 > --- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c > +++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c > @@ -309,14 +309,23 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode, > return 0; > } > > +#define DSI_PHY_DELAY(fp, vp, mbps) DIV_ROUND_UP((fp) * (mbps) + 1000 * (vp), 8000) > + > static int > dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps, > struct dw_mipi_dsi_dphy_timing *timing) > { > - timing->clk_hs2lp = 0x40; > - timing->clk_lp2hs = 0x40; > - timing->data_hs2lp = 0x40; > - timing->data_lp2hs = 0x40; > + /* > + * From STM32MP157 datasheet, valid for STM32F469, STM32F7x9, STM32H747 > + * phy_clkhs2lp_time = (272+136*UI)/(8*UI) > + * phy_clklp2hs_time = (512+40*UI)/(8*UI) > + * phy_hs2lp_time = (192+64*UI)/(8*UI) > + * phy_lp2hs_time = (256+32*UI)/(8*UI) > + */ > + timing->clk_hs2lp = DSI_PHY_DELAY(272, 136, lane_mbps); > + timing->clk_lp2hs = DSI_PHY_DELAY(512, 40, lane_mbps); > + timing->data_hs2lp = DSI_PHY_DELAY(192, 64, lane_mbps); > + timing->data_lp2hs = DSI_PHY_DELAY(256, 32, lane_mbps); Many thanks for your patch. Reviewed-by: Philippe Cornu Acked-by: Philippe Cornu I will apply it on drm-misc-next early next week, Philippe :-) > > return 0; > } > > base-commit: 35d283658a6196b2057be562096610c6793e1219 >