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([2a01:e0a:898:f380:f572:21f0:736:a7ca]) by smtp.gmail.com with ESMTPSA id b6-20020adfee86000000b0023677fd2657sm6571659wro.52.2022.10.31.02.51.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 31 Oct 2022 02:51:39 -0700 (PDT) Message-ID: Date: Mon, 31 Oct 2022 10:51:37 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.3 From: Neil Armstrong Reply-To: neil.armstrong@linaro.org Subject: Re: [PATCH 02/20] arm64: dts: Update cache properties for amlogic To: Pierre Gondois , linux-kernel@vger.kernel.org Cc: Rob.Herring@arm.com, Rob Herring , Krzysztof Kozlowski , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org References: <20221031091918.531607-1-pierre.gondois@arm.com> Content-Language: en-US Organization: Linaro Developer Services In-Reply-To: <20221031091918.531607-1-pierre.gondois@arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 31/10/2022 10:19, Pierre Gondois wrote: > The DeviceTree Specification v0.3 specifies that the cache node > 'compatible' and 'cache-level' properties are 'required'. Cf. > s3.8 Multi-level and Shared Cache Nodes > > The recently added init_of_cache_level() function checks > these properties. Add them if missing. Is this tied to a bindings change ? Since I'm only in CC to the 02/20 patch, I don't have the context here. Neil > > Signed-off-by: Pierre Gondois > --- > arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 1 + > arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 1 + > arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 1 + > arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 1 + > arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 1 + > arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 1 + > 6 files changed, 6 insertions(+) > > diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi > index b4000cf65a9a..d2f7cb4e5375 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi > @@ -36,6 +36,7 @@ cpu1: cpu@1 { > > l2: l2-cache0 { > compatible = "cache"; > + cache-level = <2>; > }; > }; > > diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > index 04f797b5a012..1648e67afbb6 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > @@ -105,6 +105,7 @@ cpu3: cpu@3 { > > l2: l2-cache0 { > compatible = "cache"; > + cache-level = <2>; > }; > }; > > diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi > index fb0ab27d1f64..af23d7968181 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi > @@ -50,6 +50,7 @@ cpu3: cpu@3 { > > l2: l2-cache0 { > compatible = "cache"; > + cache-level = <2>; > }; > }; > > diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi > index ee8fcae9f9f0..9978e619accc 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi > @@ -105,6 +105,7 @@ cpu103: cpu@103 { > > l2: l2-cache0 { > compatible = "cache"; > + cache-level = <2>; > }; > }; > }; > diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi > index 023a52005494..e3c12e0be99d 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi > @@ -132,6 +132,7 @@ cpu3: cpu@3 { > > l2: l2-cache0 { > compatible = "cache"; > + cache-level = <2>; > }; > }; > > diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi > index 80737731af3f..d845eb19d93d 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi > @@ -88,6 +88,7 @@ cpu3: cpu@3 { > > l2: l2-cache0 { > compatible = "cache"; > + cache-level = <2>; > }; > }; >