From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF682C433F5 for ; Wed, 13 Apr 2022 08:31:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233823AbiDMIeM (ORCPT ); Wed, 13 Apr 2022 04:34:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38048 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233800AbiDMIeK (ORCPT ); Wed, 13 Apr 2022 04:34:10 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7AF8E47ACA for ; Wed, 13 Apr 2022 01:31:49 -0700 (PDT) X-UUID: bdc0692cbb694b52b7d28332b20af60c-20220413 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:e3cfa12b-e499-4ca6-9da4-9d81953f6743,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,ACT ION:release,TS:45 X-CID-INFO: VERSION:1.1.4,REQID:e3cfa12b-e499-4ca6-9da4-9d81953f6743,OB:0,LOB: 0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,ACTIO N:release,TS:45 X-CID-META: VersionHash:faefae9,CLOUDID:881002a9-d103-4e36-82b9-b0e86991b3df,C OID:IGNORED,Recheck:0,SF:13|15|28|17|19|48,TC:nil,Content:0,EDM:-3,File:ni l,QS:0,BEC:nil X-UUID: bdc0692cbb694b52b7d28332b20af60c-20220413 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 418696542; Wed, 13 Apr 2022 16:31:43 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 13 Apr 2022 16:31:42 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 13 Apr 2022 16:31:42 +0800 Message-ID: Subject: Re: [PATCH v4, 3/4] drm/mediatek: keep dsi as LP00 before dcs cmds transfer From: CK Hu To: , , , , , , CC: , , , , , Date: Wed, 13 Apr 2022 16:31:42 +0800 In-Reply-To: <1649644308-8455-4-git-send-email-xinlei.lee@mediatek.com> References: <1649644308-8455-1-git-send-email-xinlei.lee@mediatek.com> <1649644308-8455-4-git-send-email-xinlei.lee@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Xinlei: On Mon, 2022-04-11 at 10:31 +0800, xinlei.lee@mediatek.com wrote: > From: Jitao Shi > > To comply with the panel sequence, hold the mipi signal to LP00 > before the dcs cmds transmission, > and pull the mipi signal high from LP00 to LP11 until the start of > the dcs cmds transmission. > The normal panel timing is : > (1) pp1800 DC pull up > (2) avdd & avee AC pull high > (3) lcm_reset pull high -> pull low -> pull high > (4) Pull MIPI signal high (LP11) -> initial code -> send video > data(HS mode) > The power-off sequence is reversed. > If dsi is not in cmd mode, then dsi will pull the mipi signal high in > the mtk_output_dsi_enable function. > > Fixes: 2dd8075d2185 ("drm/mediatek: mtk_dsi: Use the drm_panel_bridge > API") > > Signed-off-by: Jitao Shi > Signed-off-by: Xinlei Lee > --- > drivers/gpu/drm/mediatek/mtk_dsi.c | 28 +++++++++++++++++++++------- > 1 file changed, 21 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c > b/drivers/gpu/drm/mediatek/mtk_dsi.c > index cf76c53a1af6..9ad6f08c8bfe 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c > @@ -203,6 +203,7 @@ struct mtk_dsi { > struct mtk_phy_timing phy_timing; > int refcount; > bool enabled; > + bool lanes_ready; > u32 irq_data; > wait_queue_head_t irq_wait_queue; > const struct mtk_dsi_driver_data *driver_data; > @@ -654,13 +655,6 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) > mtk_dsi_config_vdo_timing(dsi); > mtk_dsi_set_interrupt_enable(dsi); > > - mtk_dsi_rxtx_control(dsi); > - usleep_range(30, 100); > - mtk_dsi_reset_dphy(dsi); > - mtk_dsi_clk_ulp_mode_leave(dsi); > - mtk_dsi_lane0_ulp_mode_leave(dsi); > - mtk_dsi_clk_hs_mode(dsi, 0); > - > return 0; > err_disable_engine_clk: > clk_disable_unprepare(dsi->engine_clk); > @@ -689,6 +683,23 @@ static void mtk_dsi_poweroff(struct mtk_dsi > *dsi) > clk_disable_unprepare(dsi->digital_clk); > > phy_power_off(dsi->phy); > + > + dsi->lanes_ready = false; > +} > + > +static void mtk_dsi_lane_ready(struct mtk_dsi *dsi) > +{ > + if (!dsi->lanes_ready) { > + dsi->lanes_ready = true; > + mtk_dsi_rxtx_control(dsi); > + usleep_range(30, 100); > + mtk_dsi_reset_dphy(dsi); > + mtk_dsi_clk_ulp_mode_leave(dsi); > + mtk_dsi_lane0_ulp_mode_leave(dsi); > + mtk_dsi_clk_hs_mode(dsi, 0); > + msleep(20); > + } else > + DRM_DEBUG("The dsi_lane is ready\n"); > } > > static void mtk_output_dsi_enable(struct mtk_dsi *dsi) > @@ -696,6 +707,7 @@ static void mtk_output_dsi_enable(struct mtk_dsi > *dsi) > if (dsi->enabled) > return; > > + mtk_dsi_lane_ready(dsi); > mtk_dsi_set_mode(dsi); > mtk_dsi_clk_hs_mode(dsi, 1); > > @@ -1001,6 +1013,8 @@ static ssize_t mtk_dsi_host_transfer(struct > mipi_dsi_host *host, > if (MTK_DSI_HOST_IS_READ(msg->type)) > irq_flag |= LPRX_RD_RDY_INT_FLAG; > > + mtk_dsi_lane_ready(dsi); In [1], YT has move mtk_dsi_lane_ready() before panel prepare for dsi- >panel case. Now you move mtk_dsi_lane_ready() after panel prepare, this may break dsi->panel case. Please provide a solution for both case. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek/mtk_dsi.c?h=v5.18-rc2&id=0707632b5bacc490f58dfbad741d586c06595ff3 Regards, CK > + > ret = mtk_dsi_host_send_cmd(dsi, msg, irq_flag); > if (ret) > goto restore_dsi_mode;