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[68.101.123.102]) by smtp.gmail.com with ESMTPSA id g79sm2835535pfd.144.2019.04.26.20.11.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 26 Apr 2019 20:11:51 -0700 (PDT) Subject: Re: [PATCH v2 1/2] net: phy: realtek: Add rtl8211e rx/tx delays config To: Serge Semin , Andrew Lunn Cc: Heiner Kallweit , "David S. Miller" , Serge Semin , netdev@vger.kernel.org, linux-kernel@vger.kernel.org References: <20190426093010.9609-1-fancer.lancer@gmail.com> <20190426212112.5624-1-fancer.lancer@gmail.com> <20190426214050.GU4041@lunn.ch> <20190426234503.y6nm5hekyclmgftc@mobilestation> From: Florian Fainelli Openpgp: preference=signencrypt Message-ID: Date: Fri, 26 Apr 2019 20:11:50 -0700 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <20190426234503.y6nm5hekyclmgftc@mobilestation> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 4/26/2019 4:45 PM, Serge Semin wrote: > On Fri, Apr 26, 2019 at 11:40:50PM +0200, Andrew Lunn wrote: >> On Sat, Apr 27, 2019 at 12:21:11AM +0300, Serge Semin wrote: >>> There are two chip pins named TXDLY and RXDLY which actually adds the 2ns >>> delays to TXC and RXC for TXD/RXD latching. Alas this is the only >>> documented info regarding the RGMII timing control configurations the PHY >>> provides. It turns out the same settings can be setup via MDIO registers >>> hidden in the extension pages layout. Particularly the extension page 0xa4 >>> provides a register 0x1c, which bits 1 and 2 control the described delays. >>> They are used to implement the "rgmii-{id,rxid,txid}" phy-mode. >>> >>> The hidden RGMII configs register utilization was found in the rtl8211e >>> U-boot driver: >>> https://elixir.bootlin.com/u-boot/v2019.01/source/drivers/net/phy/realtek.c#L99 >>> >>> There is also a freebsd-folks discussion regarding this register: >>> https://reviews.freebsd.org/D13591 >>> >>> It confirms that the register bits field must control the so called >>> configuration pins described in the table 12-13 of the official PHY >>> datasheet: >>> 8:6 = PHY Address >>> 5:4 = Auto-Negotiation >>> 3 = Interface Mode Select >>> 2 = RX Delay >>> 1 = TX Delay >>> 0 = SELRGV >>> >>> Signed-off-by: Serge Semin >> >> >> Hi Serge >> >> Next time please include a patch 0 containing a cover note explaining >> the who series. >> > > Sure as long as the patchset gets to be much bigger than two small > patches with an obvious reason to be merged. netdev likes to have a cover letter for patch count >= 1, probably something to be added to netdev-FAQ.rst. -- Florian