From: okukatla@codeaurora.org
To: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: georgi.djakov@linaro.org, evgreen@google.com,
Andy Gross <agross@kernel.org>, Rob Herring <robh+dt@kernel.org>,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, sboyd@kernel.org,
mdtipton@codeaurora.org, sibis@codeaurora.org,
saravanak@google.com, seansw@qti.qualcomm.com, elder@linaro.org,
linux-pm@vger.kernel.org, linux-arm-msm-owner@vger.kernel.org
Subject: Re: [v8 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider
Date: Mon, 01 Nov 2021 19:09:56 +0530 [thread overview]
Message-ID: <fc4ef5ecd91401f49411cf138b0da526@codeaurora.org> (raw)
In-Reply-To: <YXsxxd7f/FaDJEMa@ripper>
On 2021-10-29 04:57, Bjorn Andersson wrote:
> On Thu 21 Oct 03:40 PDT 2021, Odelu Kukatla wrote:
>
>> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280
>> SoCs.
>>
>> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
>> ---
>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++++++
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index d74a4c8..0b55742 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -3687,6 +3687,14 @@
>> };
>> };
>>
>> + epss_l3: interconnect@18590000 {
>> + compatible = "qcom,sc7280-epss-l3";
>> + reg = <0 0x18590000 0 0x1000>;
>
> This series looks like I would expect, with and without per-core dcvs.
> But can you please explain why this contradict what Sibi says here:
> https://lore.kernel.org/all/1627581885-32165-3-git-send-email-sibis@codeaurora.org/
>
> Regards,
> Bjorn
>
Thanks for Review!
Sibi's patch will be dropped, it is not required with my updated patch
series:
https://lore.kernel.org/all/1627581885-32165-3-git-send-email-sibis@codeaurora.org/
>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
>> + clock-names = "xo", "alternate";
>> + #interconnect-cells = <1>;
>> + };
>> +
>> cpufreq_hw: cpufreq@18591000 {
>> compatible = "qcom,cpufreq-epss";
>> reg = <0 0x18591000 0 0x1000>,
>> --
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
>> Forum,
>> a Linux Foundation Collaborative Project
>>
next prev parent reply other threads:[~2021-11-01 13:40 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-21 10:40 [v8 0/3] Add L3 provider support for SC7280 Odelu Kukatla
2021-10-21 10:40 ` [v8 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 Odelu Kukatla
2021-10-27 16:59 ` Rob Herring
2021-10-28 22:13 ` Stephen Boyd
2021-10-21 10:40 ` [v8 2/3] interconnect: qcom: Add EPSS L3 support " Odelu Kukatla
2021-10-28 22:13 ` Stephen Boyd
2021-11-18 20:53 ` Bjorn Andersson
2021-11-22 15:25 ` Georgi Djakov
2021-10-21 10:40 ` [v8 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider Odelu Kukatla
2021-10-28 22:14 ` Stephen Boyd
2021-10-28 23:27 ` Bjorn Andersson
2021-11-01 13:39 ` okukatla [this message]
2021-11-22 15:25 ` Georgi Djakov
2022-02-24 20:54 ` (subset) " Bjorn Andersson
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