From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752173AbcI3IC2 (ORCPT ); Fri, 30 Sep 2016 04:02:28 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:18300 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751006AbcI3ICO (ORCPT ); Fri, 30 Sep 2016 04:02:14 -0400 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 30 Sep 2016 01:02:12 -0700 Subject: Re: [PATCH v2 3/6] dt/bindings: Add bindings for Tegra GMI controller To: Mirza Krak , Rob Herring References: <1472045838-22628-1-git-send-email-mirza.krak@gmail.com> <1472045838-22628-4-git-send-email-mirza.krak@gmail.com> <20160830170636.GA8741@rob-hp-laptop> CC: Stephen Warren , Thierry Reding , Alexandre Courbot , , , Prashant Gaikwad , Michael Turquette , , , , , linux-kernel , , From: Jon Hunter Message-ID: Date: Fri, 30 Sep 2016 09:02:00 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 MIME-Version: 1.0 In-Reply-To: X-Originating-IP: [10.21.132.102] X-ClientProxiedBy: DRUKMAIL102.nvidia.com (10.25.59.20) To UKMAIL101.nvidia.com (10.26.138.13) Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Rob, On 19/09/16 08:21, Mirza Krak wrote: > 2016-09-06 12:32 GMT+02:00 Jon Hunter : >> >> On 31/08/16 12:22, Mirza Krak wrote: >>> 2016-08-30 19:06 GMT+02:00 Rob Herring : >> >> ... >> >>>>> nvidia,snor-cs = <4>; >>>> >>>> NAK, no custom CS properties. >> >> Ok, so ... >> >>> gmi@70090000 { >>> compatible = "nvidia,tegra20-gmi"; >>> reg = <0x70009000 0x1000>; >>> #address-cells = <2>; >>> #size-cells = <1>; >>> clocks = <&tegra_car TEGRA20_CLK_NOR>; >>> clock-names = "gmi"; >>> resets = <&tegra_car 42>; >>> reset-names = "gmi"; >>> ranges = <4 0 0xd0000000 0xfffffff>; >>> >>> status = "okay"; >>> >>> bus@4,0 { >>> compatible = "simple-bus"; >>> #address-cells = <1>; >>> #size-cells = <1>; >>> ranges = <0 4 0 0x40000>; >>> >>> nvidia,snor-mux-mode; >>> nvidia,snor-adv-inv; >>> >>> can@0 { >>> reg = <0 0x100>; >>> ... >>> }; >>> >>> can@40000 { >>> reg = <0x40000 0x100>; >>> ... >>> }; >>> }; >>> }; >>> >>> Have I understood you correct? >>> >>> Also wanted to verify the example case where you only have on device >>> connected to one CS#, from what I see in other implementations it >>> seems OK to put the CS# in the reg property in that case. Is this >>> correct? >>> >>> Example with one SJA1000 CAN controller connected to the GMI bus >>> on CS4: >>> >>> gmi@70090000 { >>> compatible = "nvidia,tegra20-gmi"; >>> reg = <0x70009000 0x1000>; >>> #address-cells = <2>; >>> #size-cells = <1>; >>> clocks = <&tegra_car TEGRA20_CLK_NOR>; >>> clock-names = "gmi"; >>> resets = <&tegra_car 42>; >>> reset-names = "gmi"; >>> ranges = <4 0 0xd0000000 0xfffffff>; >>> >>> status = "okay"; >>> >>> can@4,0 { >>> reg = <4 0 0x100>; >>> nvidia,snor-mux-mode; >>> nvidia,snor-adv-inv; >>> ... >>> }; >>> }; >>> >>> Jon, to be able to handle both cases in the driver we would first >>> attempt to decode the CS# from the ranges property, and fallback to >>> reg property if no ranges are defined. Does that sound reasonable? >> >> Given the above examples that may be supported, is there a >> better/simpler way to extract the CS# than what Mirza is proposing? For >> example, from the node-name unit-address? >> > > Hi. > > I have been on vacation and now I am back and wanted to finalize these > patch series. > > So pinging this thread to see I we can agree on a solution. > > Rob any comments to my proposal and Jon`s comment? Can you comment on the above? Cheers Jon -- nvpublic