From: "Liang, Kan" <kan.liang@linux.intel.com>
To: Wei Wang <wei.w.wang@intel.com>,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
pbonzini@redhat.com, ak@linux.intel.com, peterz@infradead.org
Cc: kan.liang@intel.com, mingo@redhat.com, rkrcmar@redhat.com,
like.xu@intel.com, jannh@google.com, arei.gonglei@huawei.com
Subject: Re: [PATCH v4 04/10] KVM/x86: intel_pmu_lbr_enable
Date: Tue, 8 Jan 2019 09:08:55 -0500 [thread overview]
Message-ID: <fe04d649-c3b4-ec5a-7674-20a93512c61d@linux.intel.com> (raw)
In-Reply-To: <5C343F7C.10407@intel.com>
On 1/8/2019 1:13 AM, Wei Wang wrote:
> On 01/07/2019 10:22 PM, Liang, Kan wrote:
>>
>>> Thanks for sharing. I understand the point of maintaining those
>>> models at one place,
>>> but this factor-out doesn't seem very elegant to me, like below
>>>
>>> __intel_pmu_init (int model, struct x86_pmu *x86_pmu)
>>> {
>>> ...
>>> switch (model)
>>> case INTEL_FAM6_NEHALEM:
>>> case INTEL_FAM6_NEHALEM_EP:
>>> case INTEL_FAM6_NEHALEM_EX:
>>> intel_pmu_lbr_init(x86_pmu);
>>> if (model != boot_cpu_data.x86_model)
>>> return;
>>>
>>> /* Other a lot of things init like below..*/
>>> memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
>>> sizeof(hw_cache_event_ids));
>>> memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
>>> sizeof(hw_cache_extra_regs));
>>> x86_pmu.event_constraints = intel_nehalem_event_constraints;
>>> x86_pmu.pebs_constraints =
>>> intel_nehalem_pebs_event_constraints;
>>> x86_pmu.enable_all = intel_pmu_nhm_enable_all;
>>> x86_pmu.extra_regs = intel_nehalem_extra_regs;
>>> ...
>>>
>>> Case...
>>> }
>>> We need insert "if (model != boot_cpu_data.x86_model)" in every "Case
>>> xx".
>>>
>>> What would be the rationale that we only do lbr_init for "x86_pmu"
>>> when model != boot_cpu_data.x86_model?
>>> (It looks more like a workaround to factor-out the function and get
>>> what we want)
>>
>> I thought the new function may be extended to support fake pmu as below.
>> It's not only for lbr. PMU has many CPU specific features. It can be
>> used for other features, if you want to check the compatibility in
>> future. But I don't have an example now.
>>
>> __intel_pmu_init (int model, struct x86_pmu *x86_pmu)
>> {
>> bool fake_pmu = (model != boot_cpu_data.x86_model) ? true : false;
>> ...
>> switch (model)
>> case INTEL_FAM6_NEHALEM:
>> case INTEL_FAM6_NEHALEM_EP:
>> case INTEL_FAM6_NEHALEM_EX:
>> intel_pmu_lbr_init(x86_pmu);
>> x86_pmu->event_constraints = intel_nehalem_event_constraints;
>> x86_pmu->pebs_constraints = intel_nehalem_pebs_event_constraints;
>> x86_pmu->enable_all = intel_pmu_nhm_enable_all;
>> x86_pmu->extra_regs = intel_nehalem_extra_regs;
>>
>> if (fake_pmu)
>> return;
>
> It looks similar as the one I shared above, the difference is that more
> things
> (e.g. constraints) are assigned to x86_fake_pmu.
> I'm not sure about the logic behind it (still look like a workaround).
The fake x86_pmu will include all the supported features in host. If you
want to check other features in future, it would be useful.
>
>
>
>>
>> /* Global variables should not be updated for fake PMU */
>> memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
>> sizeof(hw_cache_event_ids));
>> memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
>> sizeof(hw_cache_extra_regs));
>>
>>
>>>
>>> I would prefer having them separated as this patch for now - it is
>>> logically more clear to me.
>>>
>>
>> But it will be a problem for maintenance. Perf developer probably
>> forget to update the list in KVM. I think you have to regularly check
>> the perf code.
>>
>
> It's been very common in hypervisor development. That's why we have
> hypervisor developers here.
> When a new platform is added, we will definitely get some work like this
> to do.
>
If that's part of your job, I'm OK with it.
Thanks,
Kan
next prev parent reply other threads:[~2019-01-08 14:09 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-26 9:25 [PATCH v4 00/10] Guest LBR Enabling Wei Wang
2018-12-26 9:25 ` [PATCH v4 01/10] perf/x86: fix the variable type of the LBR MSRs Wei Wang
2018-12-26 9:25 ` [PATCH v4 02/10] perf/x86: add a function to get the lbr stack Wei Wang
2018-12-26 9:25 ` [PATCH v4 03/10] KVM/x86: KVM_CAP_X86_GUEST_LBR Wei Wang
2018-12-26 9:25 ` [PATCH v4 04/10] KVM/x86: intel_pmu_lbr_enable Wei Wang
2019-01-02 16:33 ` Liang, Kan
2019-01-04 9:58 ` Wei Wang
2019-01-04 15:57 ` Liang, Kan
2019-01-05 10:09 ` Wei Wang
2019-01-07 14:22 ` Liang, Kan
2019-01-08 6:13 ` Wei Wang
2019-01-08 14:08 ` Liang, Kan [this message]
2019-01-09 1:54 ` Wei Wang
2019-01-02 23:26 ` Jim Mattson
2019-01-03 7:22 ` Wei Wang
2019-01-03 15:34 ` Jim Mattson
2019-01-03 17:18 ` Andi Kleen
2019-01-04 10:09 ` Wei Wang
2019-01-04 15:53 ` Jim Mattson
2019-01-05 10:15 ` Wang, Wei W
2018-12-26 9:25 ` [PATCH v4 05/10] KVM/x86: expose MSR_IA32_PERF_CAPABILITIES to the guest Wei Wang
2019-01-02 23:40 ` Jim Mattson
2019-01-03 8:00 ` Wei Wang
2019-01-03 15:25 ` Jim Mattson
2019-01-07 9:15 ` Wei Wang
2019-01-07 18:05 ` Jim Mattson
2019-01-07 18:20 ` Andi Kleen
2019-01-07 18:48 ` Jim Mattson
2019-01-07 20:14 ` Andi Kleen
2019-01-07 21:00 ` Jim Mattson
2019-01-08 7:53 ` Wei Wang
2019-01-08 17:19 ` Jim Mattson
2018-12-26 9:25 ` [PATCH v4 06/10] perf/x86: no counter allocation support Wei Wang
2018-12-26 9:25 ` [PATCH v4 07/10] KVM/x86/vPMU: Add APIs to support host save/restore the guest lbr stack Wei Wang
2018-12-26 9:25 ` [PATCH v4 08/10] perf/x86: save/restore LBR_SELECT on vCPU switching Wei Wang
2018-12-26 9:25 ` [PATCH v4 09/10] perf/x86: function to check lbr user callstack mode Wei Wang
2018-12-26 9:25 ` [PATCH v4 10/10] KVM/x86/lbr: lazy save the guest lbr stack Wei Wang
2018-12-27 20:51 ` Andi Kleen
2018-12-28 3:47 ` Wei Wang
2018-12-28 19:10 ` Andi Kleen
2018-12-27 20:52 ` [PATCH v4 10/10] KVM/x86/lbr: lazy save the guest lbr stack II Andi Kleen
2018-12-29 4:25 ` Wang, Wei W
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