From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04E92C4360C for ; Sun, 29 Sep 2019 17:40:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CBD8221925 for ; Sun, 29 Sep 2019 17:40:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730518AbfI2RkM (ORCPT ); Sun, 29 Sep 2019 13:40:12 -0400 Received: from mx2.mailbox.org ([80.241.60.215]:33536 "EHLO mx2.mailbox.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730266AbfI2RkG (ORCPT ); Sun, 29 Sep 2019 13:40:06 -0400 Received: from smtp2.mailbox.org (smtp1.mailbox.org [IPv6:2001:67c:2050:105:465:1:1:0]) (using TLSv1.2 with cipher ECDHE-RSA-CHACHA20-POLY1305 (256/256 bits)) (No client certificate requested) by mx2.mailbox.org (Postfix) with ESMTPS id 8D7E2A1BDC; Sun, 29 Sep 2019 19:40:00 +0200 (CEST) X-Virus-Scanned: amavisd-new at heinlein-support.de Received: from smtp2.mailbox.org ([80.241.60.240]) by spamfilter01.heinlein-hosting.de (spamfilter01.heinlein-hosting.de [80.241.56.115]) (amavisd-new, port 10030) with ESMTP id RUpa3_VXc25g; Sun, 29 Sep 2019 19:39:55 +0200 (CEST) Subject: Re: [PATCH AUTOSEL 5.2 17/42] MIPS: lantiq: update the clock alias' for the mainline PCIe PHY driver To: Sasha Levin , linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Martin Blumenstingl , Paul Burton , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, john@phrozen.org, kishon@ti.com, ralf@linux-mips.org, robh+dt@kernel.org, mark.rutland@arm.com, ms@dev.tdt.de References: <20190929173244.8918-1-sashal@kernel.org> <20190929173244.8918-17-sashal@kernel.org> From: Hauke Mehrtens Openpgp: preference=signencrypt Autocrypt: addr=hauke@hauke-m.de; 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micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="vqoTqJDMAjIg6ueVBxDecZGi6pvZH2A4r" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --vqoTqJDMAjIg6ueVBxDecZGi6pvZH2A4r Content-Type: multipart/mixed; boundary="tCCip87R52w8X4Q5c7TDn45CxU5mAHeAK"; protected-headers="v1" From: Hauke Mehrtens To: Sasha Levin , linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Martin Blumenstingl , Paul Burton , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, john@phrozen.org, kishon@ti.com, ralf@linux-mips.org, robh+dt@kernel.org, mark.rutland@arm.com, ms@dev.tdt.de Message-ID: Subject: Re: [PATCH AUTOSEL 5.2 17/42] MIPS: lantiq: update the clock alias' for the mainline PCIe PHY driver References: <20190929173244.8918-1-sashal@kernel.org> <20190929173244.8918-17-sashal@kernel.org> In-Reply-To: <20190929173244.8918-17-sashal@kernel.org> --tCCip87R52w8X4Q5c7TDn45CxU5mAHeAK Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: quoted-printable On 9/29/19 7:32 PM, Sasha Levin wrote: > From: Martin Blumenstingl >=20 > [ Upstream commit ed90302be64a53d9031c8ce05428c358b16a5d96 ] >=20 > The mainline PCIe PHY driver has it's own devicetree node. Update the > clock alias so the mainline driver finds the clocks. >=20 > The first PCIe PHY is located at 0x1f106800 and exists on VRX200, ARX30= 0 > and GRX390. > The second PCIe PHY is located at 0x1f700400 and exists on ARX300 and > GRX390. > The third PCIe PHY is located at 0x1f106a00 and exists onl on GRX390. > Lantiq's board support package (called "UGW") names these registers > "PDI". >=20 > Signed-off-by: Martin Blumenstingl = > Signed-off-by: Paul Burton > Cc: linux-mips@vger.kernel.org > Cc: devicetree@vger.kernel.org > Cc: john@phrozen.org > Cc: kishon@ti.com > Cc: ralf@linux-mips.org > Cc: robh+dt@kernel.org > Cc: linux-kernel@vger.kernel.org > Cc: hauke@hauke-m.de > Cc: mark.rutland@arm.com > Cc: ms@dev.tdt.de > Signed-off-by: Sasha Levin > --- > arch/mips/lantiq/xway/sysctrl.c | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) Hi Sasha, This change only makes sense with the new upstream PCIe phy driver which was added to kernel 5.4 [0], older kernel versions do not have this PCIe PHY driver. I would not backport these changes to older kernel versions. [0]: https://git.kernel.org/linus/e52a632195bf43d1a91ae699e7536a6ead736aa= 7 Hauke --tCCip87R52w8X4Q5c7TDn45CxU5mAHeAK-- --vqoTqJDMAjIg6ueVBxDecZGi6pvZH2A4r Content-Type: application/pgp-signature; name="signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAEBCgAdFiEEyz0/uAcd+JwXmwtD8bdnhZyy68cFAl2Q7GUACgkQ8bdnhZyy 68cvowgAll6A19TIk6q/0VGvrhPBHP0XaBlVjuzvZjgKHGmrmViFb8fesc2v6i6r KqJ3y9WX2Y2nhxNXQYTC16moUp2uDFASAWZNfQScUg01hIuLKe04CDqHGPWv3rc3 qHYNxUR9nMZojXormiaRIt0t3zGQ5LXSMSb+6hN9Bils2o8aAduI8qPJX09wecg8 dpRj70JZyRyZvESXaCzfJEB8DNNGJhx31m7gz0IKTEM9oKp4AUvKxeoAUw1Kgli4 KDHjfCY5KyYXVaF6sUbprBmULWtOICj5Vr9mJ+EB7uI5vkT90QmtlZ1koEIKd6SN hogxu60ae+dR7jJaEFPp087Y3ne5Yg== =jZKA -----END PGP SIGNATURE----- --vqoTqJDMAjIg6ueVBxDecZGi6pvZH2A4r--