From: Denys Vlasenko <dvlasenk@redhat.com>
To: Paolo Bonzini <pbonzini@redhat.com>,
Linus Torvalds <torvalds@linux-foundation.org>
Cc: "Andy Lutomirski" <luto@amacapital.net>,
"Sara Sharon" <sara.sharon@intel.com>,
"Dan Williams" <dan.j.williams@intel.com>,
"Christian König" <christian.koenig@amd.com>,
"Vinod Koul" <vinod.koul@intel.com>,
"Alex Deucher" <alexander.deucher@amd.com>,
"Johannes Berg" <johannes.berg@intel.com>,
"Rafael J. Wysocki" <rafael.j.wysocki@intel.com>,
"Andy Lutomirski" <luto@kernel.org>,
"the arch/x86 maintainers" <x86@kernel.org>,
"Ingo Molnar" <mingo@kernel.org>,
LKML <linux-kernel@vger.kernel.org>,
"Adrian Hunter" <adrian.hunter@intel.com>
Subject: Re: RFC: Petition Intel/AMD to add POPF_IF insn
Date: Wed, 31 Aug 2016 13:12:00 +0200 [thread overview]
Message-ID: <fea16f6c-8afc-a694-cd76-c385308e1f9b@redhat.com> (raw)
In-Reply-To: <f91d4c19-688b-ff13-8905-377c0f5cea77@redhat.com>
On 08/19/2016 12:54 PM, Paolo Bonzini wrote:
> On 18/08/2016 19:24, Linus Torvalds wrote:
>>>> I didn't do CPL0 tests yet. Realized that cli/sti can be tested in userspace
>>>> if we set iopl(3) first.
>> Yes, but it might not be the same. So the timings could be very
>> different from a cpl0 case.
>
> FWIW I recently measured around 20 cycles for a popf as well on
> Haswell-EP and CPL=0 (that was for commit f2485b3e0c6c, "KVM: x86: use
> guest_exit_irqoff", 2016-07-01).
Thanks for confirmation.
I revisited benchmarking of the
if (flags & X86_EFLAGS_IF)
native_irq_enable();
patch. In "make -j20" kernel compiles on a 8-way (HT) CPU, it shows some ~5 second
improvement during ~16 minute compile. That's 0.5% speedup. It's ok, but not
something to bee too excited.
80 e6 02 and $0x2,%dh
74 01 je ffffffff810101ae <intel_pt_handle_vmx+0x3e>
fb sti
41 f6 86 91 00 00 00 02 testb $0x2,0x91(%r14)
74 01 je ffffffff81013ce7 <math_error+0x77>
fb sti
f6 83 91 00 00 00 02 testb $0x2,0x91(%rbx)
74 01 je ffffffff81013efa <do_int3+0xba>
fb sti
41 f7 c4 00 02 00 00 test $0x200,%r12d
74 01 je ffffffff8101615d <oops_end+0x5d>
fb sti
Here we trade 20-cycle POPF for either 4-cycle STI, or a branch (which is either
~1 cycle if predicted, or ~20 cycles if mispredicted). The disassembly of
vmlinux shows that gcc generates these asm patterns:
I still think a dedicated instruction for a conditional STI is worth asking for.
Along the lines of "If bit 9 in the r/m argument is set, then STI, else nothing".
What do people from CPU companies say?
next prev parent reply other threads:[~2016-08-31 11:12 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-17 17:20 RFC: Petition Intel/AMD to add POPF_IF insn Denys Vlasenko
2016-08-17 17:30 ` Christian König
2016-08-17 18:34 ` Denys Vlasenko
2016-08-17 17:32 ` Linus Torvalds
2016-08-17 18:41 ` Denys Vlasenko
[not found] ` <CA+55aFwmxwQBkyDjombS4cy1q=a_buhmDjDnaa8rdC8ZDaDYEA@mail.gmail.com>
2016-08-17 19:13 ` Andy Lutomirski
2016-08-17 19:26 ` Denys Vlasenko
2016-08-17 19:32 ` Linus Torvalds
2016-08-17 19:35 ` Denys Vlasenko
2016-08-17 19:54 ` Linus Torvalds
2016-08-17 19:37 ` Linus Torvalds
2016-08-17 21:26 ` Linus Torvalds
2016-08-17 21:35 ` Linus Torvalds
2016-08-17 21:43 ` Andy Lutomirski
2016-08-17 21:48 ` Linus Torvalds
2016-08-18 13:26 ` Denys Vlasenko
2016-08-18 17:24 ` Linus Torvalds
2016-08-18 17:47 ` Denys Vlasenko
2016-08-18 17:49 ` Denys Vlasenko
2016-08-19 10:54 ` Paolo Bonzini
2016-08-31 11:12 ` Denys Vlasenko [this message]
2016-08-18 9:21 ` Denys Vlasenko
2016-08-18 12:18 ` Denys Vlasenko
2016-08-18 17:22 ` Paolo Bonzini
2016-08-17 19:29 ` Linus Torvalds
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