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Tue, 12 Mar 2024 02:17:51 -0700 (PDT) Received: from mobilestation ([178.176.56.174]) by smtp.gmail.com with ESMTPSA id f9-20020a05651c02c900b002d2a710f864sm1521827ljo.24.2024.03.12.02.17.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 02:17:51 -0700 (PDT) Date: Tue, 12 Mar 2024 12:17:48 +0300 From: Serge Semin To: Manivannan Sadhasivam Cc: Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Marek Vasut , Yoshihiro Shimoda , Kishon Vijay Abraham I , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-msm@vger.kernel.org, mhi@lists.linux.dev, Siddharth Vadapalli , Frank Li Subject: Re: [PATCH v4 2/5] PCI: dwc: Skip finding eDMA channels count for HDMA platforms Message-ID: References: <20240306-dw-hdma-v4-0-9fed506e95be@linaro.org> <20240306-dw-hdma-v4-2-9fed506e95be@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240306-dw-hdma-v4-2-9fed506e95be@linaro.org> On Wed, Mar 06, 2024 at 03:51:58PM +0530, Manivannan Sadhasivam wrote: > In the case of Hyper DMA (HDMA) present in DWC controllers, there is no way > the drivers can auto detect the number of read/write channels as like its > predecessor embedded DMA (eDMA). So the glue drivers making use of HDMA > have to pass the channels count during probe. > > To accommodate that, let's skip the existing auto detection of channels > count procedure for HDMA based platforms. If the channels count passed by > the glue drivers were wrong in any form, then the existing sanity check > will catch it. > > Suggested-by: Serge Semin > Reviewed-by: Siddharth Vadapalli > Reviewed-by: Frank Li > Signed-off-by: Manivannan Sadhasivam Reviewed-by: Serge Semin Please find a tiny nitpick further below. > --- > drivers/pci/controller/dwc/pcie-designware.c | 15 ++++++++++----- > 1 file changed, 10 insertions(+), 5 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > index 3a26dfc5368f..599991b7ffb2 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.c > +++ b/drivers/pci/controller/dwc/pcie-designware.c > @@ -927,13 +927,18 @@ static int dw_pcie_edma_find_channels(struct dw_pcie *pci) > { > u32 val; > > - if (pci->edma.mf == EDMA_MF_EDMA_LEGACY) > - val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL); > - else > + /* > + * Autodetect the read/write channels count only for non-HDMA platforms. > + * HDMA platforms doesn't support autodetect, so the glue drivers should've > + * passed the valid count already. If not, the below sanity check will > + * catch it. > + */ This is correct for the _native_ HDMA CSRs mapping. I suggest to emphasize that in the note above. -Serge(y) > + if (pci->edma.mf != EDMA_MF_HDMA_NATIVE) { > val = dw_pcie_readl_dma(pci, PCIE_DMA_CTRL); > > - pci->edma.ll_wr_cnt = FIELD_GET(PCIE_DMA_NUM_WR_CHAN, val); > - pci->edma.ll_rd_cnt = FIELD_GET(PCIE_DMA_NUM_RD_CHAN, val); > + pci->edma.ll_wr_cnt = FIELD_GET(PCIE_DMA_NUM_WR_CHAN, val); > + pci->edma.ll_rd_cnt = FIELD_GET(PCIE_DMA_NUM_RD_CHAN, val); > + } > > /* Sanity check the channels count if the mapping was incorrect */ > if (!pci->edma.ll_wr_cnt || pci->edma.ll_wr_cnt > EDMA_MAX_WR_CH || > > -- > 2.25.1 >