From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754632AbcBPJ0U (ORCPT ); Tue, 16 Feb 2016 04:26:20 -0500 Received: from ni.piap.pl ([195.187.100.4]:42801 "EHLO ni.piap.pl" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754321AbcBPJ0R (ORCPT ); Tue, 16 Feb 2016 04:26:17 -0500 From: khalasa@piap.pl (Krzysztof =?utf-8?Q?Ha=C5=82asa?=) To: Arnd Bergmann Cc: linux-arm-kernel@lists.infradead.org, Felipe Balbi , Greg Kroah-Hartman , linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, Felipe Balbi , Haojian Zhuang , Daniel Mack , Imre Kaloz , Robert Jarzmik Subject: Re: [PATCH 3/7] usb: gadget: pxa25x_udc: use readl/writel for mmio References: <1453997722-3489596-1-git-send-email-arnd@arndb.de> <2926427.2IOxhm2GZo@wuerfel> <4239208.KBB6rfivoa@wuerfel> Date: Tue, 16 Feb 2016 10:26:14 +0100 In-Reply-To: <4239208.KBB6rfivoa@wuerfel> (Arnd Bergmann's message of "Mon, 15 Feb 2016 17:12:54 +0100") Message-ID: MIME-Version: 1.0 Content-Type: text/plain X-KLMS-Rule-ID: 1 X-KLMS-Message-Action: clean X-KLMS-AntiSpam-Lua-Profiles: 91383 [Feb 16 2016] X-KLMS-AntiSpam-Version: 5.5.9.33 X-KLMS-AntiSpam-Envelope-From: khalasa@piap.pl X-KLMS-AntiSpam-Rate: 0 X-KLMS-AntiSpam-Status: not_detected X-KLMS-AntiSpam-Method: none X-KLMS-AntiSpam-Moebius-Timestamps: 3964759, 3964778, 3964653 X-KLMS-AntiSpam-Info: LuaCore: 412 412 4b6b6fc5d3af82f77698bd9ab71b5a4bf748b220, Auth:dkim=none X-KLMS-AntiSpam-Interceptor-Info: scan successful X-KLMS-AntiPhishing: Clean, 2016/02/15 14:33:11 X-KLMS-AntiVirus: Kaspersky Security 8.0 for Linux Mail Server, version 8.0.1.721, bases: 2016/02/16 02:23:00 #7171312 X-KLMS-AntiVirus-Status: Clean, skipped Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Arnd Bergmann writes: > The barriers on a spinlock synchronize between CPUs but not an external > bus, so (on some architectures) a spinlock protecting an MMIO register > does not guarantee that two CPUs doing > > spin_lock(); > __raw_writel(address); > __raw_writel(data); > spin_unlock(); > > would cause pairs of address/data to be seen on the bus. > > Of course this is meaningless on ixp4xx, as there is only one CPU. I still don't get it. If the spinlocks synchronize between CPUs, there can only be one CPU (or core) doing the pair of raw_writel(), so how would it be possible to not get the address/data pair written out? IOW, how is it different from a system with a single CPU? > On powerpc, we have in_le32/in_be32 for SoC-internal register access, > while only PCI devices are allowed to be accessed using readl(). Yeah, this seems like a sane solution. > I would suggest using an ixp4xx specific set of accessors that comes down > to either readl() or ioread32_be(), depending on whether CONFIG_CPU_BIG_ENDIAN > is set. That makes it clear that there is a magic bus involved and that it > works on this platform but not in portable code. Hmm. This is actually the opposite - while there may be some magic (swapping) in readl() and friends, there is absolutely no magic in the __raw_readl() etc. They are essentially equivalent to *(volatile u32 *)ptr. This is constant and doesn't depend on endianess, PCI, anything. -- Krzysztof Halasa Industrial Research Institute for Automation and Measurements PIAP Al. Jerozolimskie 202, 02-486 Warsaw, Poland