* [PATCH] riscv: Add SiFive drivers to rv32_defconfig
@ 2020-07-16 4:39 Bin Meng
2020-07-16 13:13 ` Anup Patel
2020-07-16 16:39 ` Alistair Francis
0 siblings, 2 replies; 5+ messages in thread
From: Bin Meng @ 2020-07-16 4:39 UTC (permalink / raw)
To: Alistair Francis, Anup Patel, Atish Patra, Palmer Dabbelt,
Paul Walmsley, linux-kernel, linux-riscv
Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
This adds SiFive drivers to rv32_defconfig, to keep in sync with the
64-bit config. This is useful when testing 32-bit kernel with QEMU
'sifive_u' 32-bit machine.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
arch/riscv/configs/rv32_defconfig | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_defconfig
index 05bbf52..8759501 100644
--- a/arch/riscv/configs/rv32_defconfig
+++ b/arch/riscv/configs/rv32_defconfig
@@ -14,6 +14,7 @@ CONFIG_CHECKPOINT_RESTORE=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
CONFIG_BPF_SYSCALL=y
+CONFIG_SOC_SIFIVE=y
CONFIG_SOC_VIRT=y
CONFIG_ARCH_RV32I=y
CONFIG_SMP=y
@@ -61,6 +62,8 @@ CONFIG_HVC_RISCV_SBI=y
CONFIG_VIRTIO_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_VIRTIO=y
+CONFIG_SPI=y
+CONFIG_SPI_SIFIVE=y
# CONFIG_PTP_1588_CLOCK is not set
CONFIG_POWER_RESET=y
CONFIG_DRM=y
@@ -76,6 +79,8 @@ CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_USB_STORAGE=y
CONFIG_USB_UAS=y
+CONFIG_MMC=y
+CONFIG_MMC_SPI=y
CONFIG_RTC_CLASS=y
CONFIG_VIRTIO_PCI=y
CONFIG_VIRTIO_BALLOON=y
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] riscv: Add SiFive drivers to rv32_defconfig
2020-07-16 4:39 [PATCH] riscv: Add SiFive drivers to rv32_defconfig Bin Meng
@ 2020-07-16 13:13 ` Anup Patel
2020-07-16 16:39 ` Alistair Francis
1 sibling, 0 replies; 5+ messages in thread
From: Anup Patel @ 2020-07-16 13:13 UTC (permalink / raw)
To: Bin Meng
Cc: Alistair Francis, Anup Patel, Atish Patra, Palmer Dabbelt,
Paul Walmsley, linux-kernel@vger.kernel.org List, linux-riscv,
Bin Meng
On Thu, Jul 16, 2020 at 10:10 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This adds SiFive drivers to rv32_defconfig, to keep in sync with the
> 64-bit config. This is useful when testing 32-bit kernel with QEMU
> 'sifive_u' 32-bit machine.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> ---
>
> arch/riscv/configs/rv32_defconfig | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_defconfig
> index 05bbf52..8759501 100644
> --- a/arch/riscv/configs/rv32_defconfig
> +++ b/arch/riscv/configs/rv32_defconfig
> @@ -14,6 +14,7 @@ CONFIG_CHECKPOINT_RESTORE=y
> CONFIG_BLK_DEV_INITRD=y
> CONFIG_EXPERT=y
> CONFIG_BPF_SYSCALL=y
> +CONFIG_SOC_SIFIVE=y
> CONFIG_SOC_VIRT=y
> CONFIG_ARCH_RV32I=y
> CONFIG_SMP=y
> @@ -61,6 +62,8 @@ CONFIG_HVC_RISCV_SBI=y
> CONFIG_VIRTIO_CONSOLE=y
> CONFIG_HW_RANDOM=y
> CONFIG_HW_RANDOM_VIRTIO=y
> +CONFIG_SPI=y
> +CONFIG_SPI_SIFIVE=y
> # CONFIG_PTP_1588_CLOCK is not set
> CONFIG_POWER_RESET=y
> CONFIG_DRM=y
> @@ -76,6 +79,8 @@ CONFIG_USB_OHCI_HCD=y
> CONFIG_USB_OHCI_HCD_PLATFORM=y
> CONFIG_USB_STORAGE=y
> CONFIG_USB_UAS=y
> +CONFIG_MMC=y
> +CONFIG_MMC_SPI=y
> CONFIG_RTC_CLASS=y
> CONFIG_VIRTIO_PCI=y
> CONFIG_VIRTIO_BALLOON=y
> --
> 2.7.4
>
Looks good to me.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] riscv: Add SiFive drivers to rv32_defconfig
2020-07-16 4:39 [PATCH] riscv: Add SiFive drivers to rv32_defconfig Bin Meng
2020-07-16 13:13 ` Anup Patel
@ 2020-07-16 16:39 ` Alistair Francis
2020-08-18 9:29 ` Bin Meng
1 sibling, 1 reply; 5+ messages in thread
From: Alistair Francis @ 2020-07-16 16:39 UTC (permalink / raw)
To: paul.walmsley, palmer, linux-riscv, Atish Patra, bmeng.cn,
Anup Patel, linux-kernel
Cc: bin.meng
On Wed, 2020-07-15 at 21:39 -0700, Bin Meng wrote:
> From: Bin Meng <bin.meng@windriver.com>
>
> This adds SiFive drivers to rv32_defconfig, to keep in sync with the
> 64-bit config. This is useful when testing 32-bit kernel with QEMU
> 'sifive_u' 32-bit machine.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> arch/riscv/configs/rv32_defconfig | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/riscv/configs/rv32_defconfig
> b/arch/riscv/configs/rv32_defconfig
> index 05bbf52..8759501 100644
> --- a/arch/riscv/configs/rv32_defconfig
> +++ b/arch/riscv/configs/rv32_defconfig
> @@ -14,6 +14,7 @@ CONFIG_CHECKPOINT_RESTORE=y
> CONFIG_BLK_DEV_INITRD=y
> CONFIG_EXPERT=y
> CONFIG_BPF_SYSCALL=y
> +CONFIG_SOC_SIFIVE=y
> CONFIG_SOC_VIRT=y
> CONFIG_ARCH_RV32I=y
> CONFIG_SMP=y
> @@ -61,6 +62,8 @@ CONFIG_HVC_RISCV_SBI=y
> CONFIG_VIRTIO_CONSOLE=y
> CONFIG_HW_RANDOM=y
> CONFIG_HW_RANDOM_VIRTIO=y
> +CONFIG_SPI=y
> +CONFIG_SPI_SIFIVE=y
> # CONFIG_PTP_1588_CLOCK is not set
> CONFIG_POWER_RESET=y
> CONFIG_DRM=y
> @@ -76,6 +79,8 @@ CONFIG_USB_OHCI_HCD=y
> CONFIG_USB_OHCI_HCD_PLATFORM=y
> CONFIG_USB_STORAGE=y
> CONFIG_USB_UAS=y
> +CONFIG_MMC=y
> +CONFIG_MMC_SPI=y
> CONFIG_RTC_CLASS=y
> CONFIG_VIRTIO_PCI=y
> CONFIG_VIRTIO_BALLOON=y
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] riscv: Add SiFive drivers to rv32_defconfig
2020-07-16 16:39 ` Alistair Francis
@ 2020-08-18 9:29 ` Bin Meng
2020-08-20 18:00 ` Palmer Dabbelt
0 siblings, 1 reply; 5+ messages in thread
From: Bin Meng @ 2020-08-18 9:29 UTC (permalink / raw)
To: Alistair Francis
Cc: paul.walmsley, palmer, linux-riscv, Atish Patra, Anup Patel,
linux-kernel, bin.meng
On Fri, Jul 17, 2020 at 12:39 AM Alistair Francis
<Alistair.Francis@wdc.com> wrote:
>
> On Wed, 2020-07-15 at 21:39 -0700, Bin Meng wrote:
> > From: Bin Meng <bin.meng@windriver.com>
> >
> > This adds SiFive drivers to rv32_defconfig, to keep in sync with the
> > 64-bit config. This is useful when testing 32-bit kernel with QEMU
> > 'sifive_u' 32-bit machine.
> >
> > Signed-off-by: Bin Meng <bin.meng@windriver.com>
>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
>
Ping?
Is this patch applied anywhere? Thanks!
Regards,
Bin
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] riscv: Add SiFive drivers to rv32_defconfig
2020-08-18 9:29 ` Bin Meng
@ 2020-08-20 18:00 ` Palmer Dabbelt
0 siblings, 0 replies; 5+ messages in thread
From: Palmer Dabbelt @ 2020-08-20 18:00 UTC (permalink / raw)
To: bmeng.cn
Cc: Alistair Francis, Paul Walmsley, linux-riscv, Atish Patra,
Anup Patel, linux-kernel, bin.meng
On Tue, 18 Aug 2020 02:29:53 PDT (-0700), bmeng.cn@gmail.com wrote:
> On Fri, Jul 17, 2020 at 12:39 AM Alistair Francis
> <Alistair.Francis@wdc.com> wrote:
>>
>> On Wed, 2020-07-15 at 21:39 -0700, Bin Meng wrote:
>> > From: Bin Meng <bin.meng@windriver.com>
>> >
>> > This adds SiFive drivers to rv32_defconfig, to keep in sync with the
>> > 64-bit config. This is useful when testing 32-bit kernel with QEMU
>> > 'sifive_u' 32-bit machine.
>> >
>> > Signed-off-by: Bin Meng <bin.meng@windriver.com>
>>
>> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
>>
>
> Ping?
>
> Is this patch applied anywhere? Thanks!
Sorry, I must have missed it. It's on fixes.
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-08-20 18:00 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2020-07-16 4:39 [PATCH] riscv: Add SiFive drivers to rv32_defconfig Bin Meng
2020-07-16 13:13 ` Anup Patel
2020-07-16 16:39 ` Alistair Francis
2020-08-18 9:29 ` Bin Meng
2020-08-20 18:00 ` Palmer Dabbelt
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