linux-kernel.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Palmer Dabbelt <palmer@dabbelt.com>
To: Linus Torvalds <torvalds@linux-foundation.org>
Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: Re: [GIT PULL] RISC-V Patches for the 5.16 Merge Window, Part 1
Date: Fri, 12 Nov 2021 09:42:03 -0800 (PST)	[thread overview]
Message-ID: <mhng-33397cc1-0e32-4947-983a-0cf6e63dcb94@palmer-ri-x1c9> (raw)
In-Reply-To: <mhng-109b0503-bc7c-4da8-8621-28aec8d9df59@palmer-ri-x1c9>

On Fri, 12 Nov 2021 09:32:15 PST (-0800), Palmer Dabbelt wrote:
> The following changes since commit 3f2401f47d29d669e2cb137709d10dd4c156a02f:
>
>   RISC-V: Add hypervisor extension related CSR defines (2021-10-04 04:54:55 -0400)
>
> are available in the Git repository at:
>
>   git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-5.16-mw1
>
> for you to fetch changes up to ffa7a9141bb70702744a312f904b190ca064bdd7:
>
>   riscv: defconfig: enable DRM_NOUVEAU (2021-10-27 14:36:09 -0700)
>
> ----------------------------------------------------------------
> RISC-V Patches for the 5.16 Merge Window, Part 1
>
> * Support for time namespaces in the VDSO, along with some associated
>   cleanups.
> * Support for building rv32 randconfigs.
> * Improvements to the XIP port that allow larger kernels to function
> * Various device tree cleanups for both the SiFive and Microchip boards
> * A handful of defconfig updates, including enabling Nouveau.
>
> There are also various small cleanups.

I forgot to send along my conflict resolutions:

    diff --cc arch/riscv/Kconfig
    index dcd7afcd98ef,a34c531be4e7..821252b65f89
    --- a/arch/riscv/Kconfig
    +++ b/arch/riscv/Kconfig
    @@@ -62,8 -62,6 +62,7 @@@ config RISC
      	select GENERIC_SCHED_CLOCK
      	select GENERIC_SMP_IDLE_THREAD
      	select GENERIC_TIME_VSYSCALL if MMU && 64BIT
     +	select GENERIC_VDSO_TIME_NS if HAVE_GENERIC_VDSO
    - 	select HANDLE_DOMAIN_IRQ
      	select HAVE_ARCH_AUDITSYSCALL
      	select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
      	select HAVE_ARCH_JUMP_LABEL_RELATIVE if !XIP_KERNEL
    diff --cc arch/riscv/Makefile
    index 9247407b95d6,7f19b784e649..5927c94302b8
    --- a/arch/riscv/Makefile
    +++ b/arch/riscv/Makefile
    @@@ -137,16 -136,3 +136,13 @@@ zinstall: install-image = Image.g
      install zinstall:
      	$(CONFIG_SHELL) $(srctree)/$(boot)/install.sh $(KERNELRELEASE) \
      	$(boot)/$(install-image) System.map "$(INSTALL_PATH)"
     +
    - archclean:
    - 	$(Q)$(MAKE) $(clean)=$(boot)
    -
     +PHONY += rv32_randconfig
     +rv32_randconfig:
     +	$(Q)$(MAKE) KCONFIG_ALLCONFIG=$(srctree)/arch/riscv/configs/32-bit.config \
     +		-f $(srctree)/Makefile randconfig
     +
     +PHONY += rv64_randconfig
     +rv64_randconfig:
     +	$(Q)$(MAKE) KCONFIG_ALLCONFIG=$(srctree)/arch/riscv/configs/64-bit.config \
     +		-f $(srctree)/Makefile randconfig
    
Sorry if anything else went off the rails, being on the new computer has 
be a bit off kilter.  I think I got all my PGP stuff sorted out 
yesterday.

>
> ----------------------------------------------------------------
> Dimitri John Ledkov (1):
>       riscv: set default pm_power_off to NULL
>
> Heinrich Schuchardt (1):
>       riscv: defconfig: enable DRM_NOUVEAU
>
> Kefeng Wang (1):
>       riscv/vdso: Drop unneeded part due to merge issue
>
> Krzysztof Kozlowski (11):
>       dt-bindings: mmc: cdns: document Microchip MPFS MMC/SDHCI controller
>       riscv: dts: microchip: drop duplicated nodes
>       riscv: dts: microchip: fix board compatible
>       riscv: dts: microchip: drop duplicated MMC/SDHC node
>       riscv: dts: microchip: drop unused pinctrl-names
>       riscv: dts: microchip: use vendor compatible for Cadence SD4HC
>       riscv: dts: sifive: use only generic JEDEC SPI NOR flash compatible
>       riscv: dts: sifive: fix Unleashed board compatible
>       riscv: dts: sifive: drop duplicated nodes and properties in sifive
>       riscv: dts: microchip: add missing compatibles for clint and plic
>       riscv: dts: sifive: add missing compatible for plic
>
> Palmer Dabbelt (3):
>       Merge remote-tracking branch 'palmer/riscv-vdso-cleanup' into for-next
>       Merge tag 'for-riscv' of https://git.kernel.org/pub/scm/virt/kvm/kvm.git into for-next
>       Merge tag 'riscv-sifive-dt-5.16' of git://gitolite.kernel.org/pub/scm/linux/kernel/git/krzk/linux into for-next
>
> Randy Dunlap (1):
>       riscv: add rv32 and rv64 randconfig build targets
>
> Tong Tiangen (1):
>       riscv/vdso: Add support for time namespaces
>
> Vineet Gupta (1):
>       riscv: mm: don't advertise 1 num_asid for 0 asid bits
>
> Vitaly Wool (1):
>       riscv: remove .text section size limitation for XIP
>
>  .../devicetree/bindings/mmc/cdns,sdhci.yaml        |   1 +
>  arch/riscv/Kconfig                                 |   1 +
>  arch/riscv/Makefile                                |  10 +
>  .../dts/microchip/microchip-mpfs-icicle-kit.dts    |  18 +-
>  arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi  |  40 +---
>  arch/riscv/boot/dts/sifive/fu540-c000.dtsi         |   2 +-
>  .../riscv/boot/dts/sifive/hifive-unleashed-a00.dts |  10 +-
>  .../riscv/boot/dts/sifive/hifive-unmatched-a00.dts |   7 +-
>  arch/riscv/configs/32-bit.config                   |   2 +
>  arch/riscv/configs/64-bit.config                   |   2 +
>  arch/riscv/configs/defconfig                       |   7 +-
>  arch/riscv/include/asm/page.h                      |   2 +
>  arch/riscv/include/asm/pgtable.h                   |   6 +-
>  arch/riscv/include/asm/syscall.h                   |   1 +
>  arch/riscv/include/asm/vdso.h                      |  13 +-
>  arch/riscv/include/asm/vdso/gettimeofday.h         |   7 +
>  arch/riscv/kernel/head.S                           |  12 +
>  arch/riscv/kernel/reset.c                          |  12 +-
>  arch/riscv/kernel/syscall_table.c                  |   1 -
>  arch/riscv/kernel/vdso.c                           | 261 +++++++++++++++++----
>  arch/riscv/kernel/vdso/vdso.lds.S                  |   6 +-
>  arch/riscv/kernel/vmlinux-xip.lds.S                |  10 +-
>  arch/riscv/mm/context.c                            |   8 +-
>  arch/riscv/mm/init.c                               |   7 +-
>  24 files changed, 311 insertions(+), 135 deletions(-)
>  create mode 100644 arch/riscv/configs/32-bit.config
>  create mode 100644 arch/riscv/configs/64-bit.config

  reply	other threads:[~2021-11-12 17:42 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-12 17:32 [GIT PULL] RISC-V Patches for the 5.16 Merge Window, Part 1 Palmer Dabbelt
2021-11-12 17:42 ` Palmer Dabbelt [this message]
2021-11-12 21:37 ` Linus Torvalds
2021-11-12 21:52   ` Palmer Dabbelt
2021-11-12 22:22     ` Andreas Schwab
2021-11-12 23:12       ` Palmer Dabbelt
2021-11-13 19:15 ` pr-tracker-bot

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=mhng-33397cc1-0e32-4947-983a-0cf6e63dcb94@palmer-ri-x1c9 \
    --to=palmer@dabbelt.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=torvalds@linux-foundation.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).