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[76.210.143.223]) by smtp.gmail.com with ESMTPSA id w143sm12602170pfc.165.2020.05.12.16.00.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 May 2020 16:00:26 -0700 (PDT) Date: Tue, 12 May 2020 16:00:26 -0700 (PDT) X-Google-Original-Date: Tue, 12 May 2020 15:59:50 PDT (-0700) Subject: Re: [PATCH 19/31] riscv: use asm-generic/cacheflush.h In-Reply-To: <20200510075510.987823-20-hch@lst.de> CC: akpm@linux-foundation.org, Arnd Bergmann , zippel@linux-m68k.org, linux-arch@vger.kernel.org, linux-xtensa@linux-xtensa.org, monstr@monstr.eu, jeyu@kernel.org, linux-ia64@vger.kernel.org, linux-c6x-dev@linux-c6x.org, linux-sh@vger.kernel.org, linux-hexagon@vger.kernel.org, x86@kernel.org, linux-um@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, linux-mm@kvack.org, linux-m68k@lists.linux-m68k.org, openrisc@lists.librecores.org, linux-alpha@vger.kernel.org, sparclinux@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-riscv@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org From: Palmer Dabbelt To: Christoph Hellwig Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, 10 May 2020 00:54:58 PDT (-0700), Christoph Hellwig wrote: > RISC-V needs almost no cache flushing routines of its own. Rely on > asm-generic/cacheflush.h for the defaults. > > Also remove the pointless __KERNEL__ ifdef while we're at it. > --- > arch/riscv/include/asm/cacheflush.h | 62 ++--------------------------- > 1 file changed, 3 insertions(+), 59 deletions(-) > > diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h > index c8677c75f82cb..a167b4fbdf007 100644 > --- a/arch/riscv/include/asm/cacheflush.h > +++ b/arch/riscv/include/asm/cacheflush.h > @@ -8,65 +8,6 @@ > > #include > > -#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0 > - > -/* > - * The cache doesn't need to be flushed when TLB entries change when > - * the cache is mapped to physical memory, not virtual memory > - */ > -static inline void flush_cache_all(void) > -{ > -} > - > -static inline void flush_cache_mm(struct mm_struct *mm) > -{ > -} > - > -static inline void flush_cache_dup_mm(struct mm_struct *mm) > -{ > -} > - > -static inline void flush_cache_range(struct vm_area_struct *vma, > - unsigned long start, > - unsigned long end) > -{ > -} > - > -static inline void flush_cache_page(struct vm_area_struct *vma, > - unsigned long vmaddr, > - unsigned long pfn) > -{ > -} > - > -static inline void flush_dcache_mmap_lock(struct address_space *mapping) > -{ > -} > - > -static inline void flush_dcache_mmap_unlock(struct address_space *mapping) > -{ > -} > - > -static inline void flush_icache_page(struct vm_area_struct *vma, > - struct page *page) > -{ > -} > - > -static inline void flush_cache_vmap(unsigned long start, unsigned long end) > -{ > -} > - > -static inline void flush_cache_vunmap(unsigned long start, unsigned long end) > -{ > -} > - > -#define copy_to_user_page(vma, page, vaddr, dst, src, len) \ > - do { \ > - memcpy(dst, src, len); \ > - flush_icache_user_range(vma, page, vaddr, len); \ > - } while (0) > -#define copy_from_user_page(vma, page, vaddr, dst, src, len) \ > - memcpy(dst, src, len) > - > static inline void local_flush_icache_all(void) > { > asm volatile ("fence.i" ::: "memory"); > @@ -79,6 +20,7 @@ static inline void flush_dcache_page(struct page *page) > if (test_bit(PG_dcache_clean, &page->flags)) > clear_bit(PG_dcache_clean, &page->flags); > } > +#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 > > /* > * RISC-V doesn't have an instruction to flush parts of the instruction cache, > @@ -105,4 +47,6 @@ void flush_icache_mm(struct mm_struct *mm, bool local); > #define SYS_RISCV_FLUSH_ICACHE_LOCAL 1UL > #define SYS_RISCV_FLUSH_ICACHE_ALL (SYS_RISCV_FLUSH_ICACHE_LOCAL) > > +#include > + > #endif /* _ASM_RISCV_CACHEFLUSH_H */ Thanks! Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Were you trying to get these all in at once, or do you want me to take it into my tree?