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[76.210.143.223]) by smtp.gmail.com with ESMTPSA id l23sm6015331pjy.22.2020.04.03.08.53.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Apr 2020 08:53:15 -0700 (PDT) Date: Fri, 03 Apr 2020 08:53:15 -0700 (PDT) X-Google-Original-Date: Fri, 03 Apr 2020 08:45:02 PDT (-0700) Subject: Re: [RFC PATCH 5/7] riscv: Use pgtable_l4_enabled to output mmu type in cpuinfo In-Reply-To: <20200322110028.18279-6-alex@ghiti.fr> CC: Paul Walmsley , zong.li@sifive.com, anup@brainfault.org, Christoph Hellwig , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, alex@ghiti.fr From: Palmer Dabbelt To: alex@ghiti.fr Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, 22 Mar 2020 04:00:26 PDT (-0700), alex@ghiti.fr wrote: > Now that the mmu type is determined at runtime using SATP > characteristic, use the global variable pgtable_l4_enabled to output > mmu type of the processor through /proc/cpuinfo instead of relying on > device tree infos. > > Signed-off-by: Alexandre Ghiti > --- > arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 4 ---- > arch/riscv/kernel/cpu.c | 24 ++++++++++++---------- > 2 files changed, 13 insertions(+), 15 deletions(-) > > diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi > index 7db861053483..6138590a2229 100644 > --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi > +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi > @@ -50,7 +50,6 @@ > i-cache-size = <32768>; > i-tlb-sets = <1>; > i-tlb-size = <32>; > - mmu-type = "riscv,sv39"; > reg = <1>; > riscv,isa = "rv64imafdc"; > tlb-split; > @@ -74,7 +73,6 @@ > i-cache-size = <32768>; > i-tlb-sets = <1>; > i-tlb-size = <32>; > - mmu-type = "riscv,sv39"; > reg = <2>; > riscv,isa = "rv64imafdc"; > tlb-split; > @@ -98,7 +96,6 @@ > i-cache-size = <32768>; > i-tlb-sets = <1>; > i-tlb-size = <32>; > - mmu-type = "riscv,sv39"; > reg = <3>; > riscv,isa = "rv64imafdc"; > tlb-split; > @@ -122,7 +119,6 @@ > i-cache-size = <32768>; > i-tlb-sets = <1>; > i-tlb-size = <32>; > - mmu-type = "riscv,sv39"; > reg = <4>; > riscv,isa = "rv64imafdc"; > tlb-split; > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > index 40a3c442ac5f..38a699b997a8 100644 > --- a/arch/riscv/kernel/cpu.c > +++ b/arch/riscv/kernel/cpu.c > @@ -8,6 +8,8 @@ > #include > #include > > +extern bool pgtable_l4_enabled; > + > /* > * Returns the hart ID of the given device tree node, or -ENODEV if the node > * isn't an enabled and valid RISC-V hart node. > @@ -54,18 +56,19 @@ static void print_isa(struct seq_file *f, const char *isa) > seq_puts(f, "\n"); > } > > -static void print_mmu(struct seq_file *f, const char *mmu_type) > +static void print_mmu(struct seq_file *f) > { > + char sv_type[16]; > + > #if defined(CONFIG_32BIT) > - if (strcmp(mmu_type, "riscv,sv32") != 0) > - return; > + strncpy(sv_type, "sv32", 5); > #elif defined(CONFIG_64BIT) > - if (strcmp(mmu_type, "riscv,sv39") != 0 && > - strcmp(mmu_type, "riscv,sv48") != 0) > - return; > + if (pgtable_l4_enabled) > + strncpy(sv_type, "sv48", 5); > + else > + strncpy(sv_type, "sv39", 5); > #endif > - > - seq_printf(f, "mmu\t\t: %s\n", mmu_type+6); > + seq_printf(f, "mmu\t\t: %s\n", sv_type); > } > > static void *c_start(struct seq_file *m, loff_t *pos) > @@ -90,14 +93,13 @@ static int c_show(struct seq_file *m, void *v) > { > unsigned long cpu_id = (unsigned long)v - 1; > struct device_node *node = of_get_cpu_node(cpu_id, NULL); > - const char *compat, *isa, *mmu; > + const char *compat, *isa; > > seq_printf(m, "processor\t: %lu\n", cpu_id); > seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id)); > if (!of_property_read_string(node, "riscv,isa", &isa)) > print_isa(m, isa); > - if (!of_property_read_string(node, "mmu-type", &mmu)) > - print_mmu(m, mmu); > + print_mmu(m); > if (!of_property_read_string(node, "compatible", &compat) > && strcmp(compat, "riscv")) > seq_printf(m, "uarch\t\t: %s\n", compat); Reviewed-by: Palmer Dabbelt