From: Palmer Dabbelt <palmer@sifive.com>
To: Anup Patel <Anup.Patel@wdc.com>
Cc: aou@eecs.berkeley.edu, Atish Patra <Atish.Patra@wdc.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Christoph Hellwig <hch@infradead.org>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Anup Patel <Anup.Patel@wdc.com>
Subject: Re: [PATCH v6 0/3] Allow accessing CSR using CSR number
Date: Tue, 30 Apr 2019 17:11:27 -0700 (PDT) [thread overview]
Message-ID: <mhng-c3baf15e-decb-4b3f-91c3-87642f14c3e4@palmer-si-x1e> (raw)
In-Reply-To: <20190425083804.11991-1-anup.patel@wdc.com>
On Thu, 25 Apr 2019 01:38:24 PDT (-0700), Anup Patel wrote:
> This patch series adds support to access CSR using both CSR name and
> CSR numbers.
>
> Also, we should prefer accessing CSRs using their CSR numbers because:
> 1. It compiles fine with older toolchains.
> 2. We can use latest CSR names in #define macro names of CSR numbers
> as-per RISC-V spec. (e.g. sptbr => CSR_SATP, sbadaddr => CSR_STVAL, etc.)
> 3. We can access newly added CSRs even if toolchain does not recognize
> newly addes CSRs by name. (e.g. BSSTATUS, BSIE, SSIP, etc.)
>
> The patchset can be found in riscv_csr_number_v6 branch of
> https//github.com/avpatel/linux.git
>
> Changes since v5:
> - Drop redundant INTERRUPT_CAUSE_FLAG from kernel/irq.c
>
> Changes since v4:
> - Express SCAUSE_IRQ_FLAG in-terms of __riscv_xlen
>
> Changes since v3:
> - Keep old INTERRUPT_xyz defines in kernel/irq.c for PATCH2
>
> Changes since v2:
> - Dropped PATCH1 which added asm/encoding.h
> - Added new PATCH1 which beautifies asm/csr.h by using tabs to
> align macro values
>
> Changes since v1:
> - Squash PATCH2 into cpatch3
> - Added new PATCH2 to add interrupt related SCAUSE defines
> in asm/encoding.h
>
> Anup Patel (3):
> RISC-V: Use tabs to align macro values in asm/csr.h
> RISC-V: Add interrupt related SCAUSE defines in asm/csr.h
> RISC-V: Access CSRs using CSR numbers
>
> arch/riscv/include/asm/csr.h | 123 +++++++++++++++++----------
> arch/riscv/include/asm/irqflags.h | 10 +--
> arch/riscv/include/asm/mmu_context.h | 7 +-
> arch/riscv/kernel/entry.S | 22 ++---
> arch/riscv/kernel/head.S | 12 +--
> arch/riscv/kernel/irq.c | 16 +---
> arch/riscv/kernel/perf_event.c | 4 +-
> arch/riscv/kernel/smp.c | 2 +-
> arch/riscv/kernel/traps.c | 6 +-
> arch/riscv/mm/fault.c | 6 +-
> 10 files changed, 111 insertions(+), 97 deletions(-)
>
> --
> 2.17.1
Thanks. I've added these to for-next with a minor merge conflict, but I think
I managed to avoid screwing it up!
prev parent reply other threads:[~2019-05-01 0:11 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-25 8:38 [PATCH v6 0/3] Allow accessing CSR using CSR number Anup Patel
2019-04-25 8:38 ` [PATCH v6 1/3] RISC-V: Use tabs to align macro values in asm/csr.h Anup Patel
2019-04-25 8:38 ` [PATCH v6 2/3] RISC-V: Add interrupt related SCAUSE defines " Anup Patel
2019-04-25 8:42 ` Christoph Hellwig
2019-04-25 8:38 ` [PATCH v6 3/3] RISC-V: Access CSRs using CSR numbers Anup Patel
2019-05-01 0:11 ` Palmer Dabbelt [this message]
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