From: tip-bot for Fenghua Yu <tipbot@zytor.com>
To: linux-tip-commits@vger.kernel.org
Cc: fenghua.yu@intel.com, linux-kernel@vger.kernel.org,
davidcc@google.com, eranian@google.com, h.peter.anvin@intel.com,
sai.praneeth.prakhya@intel.com, hpa@zytor.com,
tony.luck@intel.com, peterz@infradead.org, bp@suse.de,
ravi.v.shankar@intel.com, vikas.shivappa@linux.intel.com,
nilayvaish@gmail.com, tglx@linutronix.de, mingo@elte.hu,
shli@fb.com, mingo@kernel.org, dave.hansen@intel.com
Subject: [tip:x86/cache] x86/intel_rdt: Add Haswell feature discovery
Date: Wed, 26 Oct 2016 14:27:57 -0700 [thread overview]
Message-ID: <tip-113c60970cf41723891e3a1b303517eaf8510bb5@git.kernel.org> (raw)
In-Reply-To: <1477142405-32078-8-git-send-email-fenghua.yu@intel.com>
Commit-ID: 113c60970cf41723891e3a1b303517eaf8510bb5
Gitweb: http://git.kernel.org/tip/113c60970cf41723891e3a1b303517eaf8510bb5
Author: Fenghua Yu <fenghua.yu@intel.com>
AuthorDate: Sat, 22 Oct 2016 06:19:54 -0700
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitDate: Wed, 26 Oct 2016 23:12:38 +0200
x86/intel_rdt: Add Haswell feature discovery
Some Haswell generation CPUs support RDT, but they don't enumerate this via
CPUID. Use rdmsr_safe() and wrmsr_safe() to probe the MSRs on cpu model 63
(INTEL_FAM6_HASWELL_X)
Move the relevant defines into a common header file which is shared between
RDT/CQM and RDT/Allocation to avoid duplication.
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Cc: "Ravi V Shankar" <ravi.v.shankar@intel.com>
Cc: "Tony Luck" <tony.luck@intel.com>
Cc: "David Carrillo-Cisneros" <davidcc@google.com>
Cc: "Sai Prakhya" <sai.praneeth.prakhya@intel.com>
Cc: "Peter Zijlstra" <peterz@infradead.org>
Cc: "Stephane Eranian" <eranian@google.com>
Cc: "Dave Hansen" <dave.hansen@intel.com>
Cc: "Shaohua Li" <shli@fb.com>
Cc: "Nilay Vaish" <nilayvaish@gmail.com>
Cc: "Vikas Shivappa" <vikas.shivappa@linux.intel.com>
Cc: "Ingo Molnar" <mingo@elte.hu>
Cc: "Borislav Petkov" <bp@suse.de>
Cc: "H. Peter Anvin" <h.peter.anvin@intel.com>
Link: http://lkml.kernel.org/r/1477142405-32078-8-git-send-email-fenghua.yu@intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
arch/x86/events/intel/cqm.c | 2 +-
arch/x86/include/asm/intel_rdt.h | 6 ++++
arch/x86/include/asm/intel_rdt_common.h | 6 ++++
arch/x86/kernel/cpu/intel_rdt.c | 49 ++++++++++++++++++++++++++++++---
4 files changed, 58 insertions(+), 5 deletions(-)
diff --git a/arch/x86/events/intel/cqm.c b/arch/x86/events/intel/cqm.c
index 8f82b02..df86874 100644
--- a/arch/x86/events/intel/cqm.c
+++ b/arch/x86/events/intel/cqm.c
@@ -7,9 +7,9 @@
#include <linux/perf_event.h>
#include <linux/slab.h>
#include <asm/cpu_device_id.h>
+#include <asm/intel_rdt_common.h>
#include "../perf_event.h"
-#define MSR_IA32_PQR_ASSOC 0x0c8f
#define MSR_IA32_QM_CTR 0x0c8e
#define MSR_IA32_QM_EVTSEL 0x0c8d
diff --git a/arch/x86/include/asm/intel_rdt.h b/arch/x86/include/asm/intel_rdt.h
new file mode 100644
index 0000000..3aca86d
--- /dev/null
+++ b/arch/x86/include/asm/intel_rdt.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_X86_INTEL_RDT_H
+#define _ASM_X86_INTEL_RDT_H
+
+#define IA32_L3_CBM_BASE 0xc90
+
+#endif /* _ASM_X86_INTEL_RDT_H */
diff --git a/arch/x86/include/asm/intel_rdt_common.h b/arch/x86/include/asm/intel_rdt_common.h
new file mode 100644
index 0000000..e6e15cf
--- /dev/null
+++ b/arch/x86/include/asm/intel_rdt_common.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_X86_INTEL_RDT_COMMON_H
+#define _ASM_X86_INTEL_RDT_COMMON_H
+
+#define MSR_IA32_PQR_ASSOC 0x0c8f
+
+#endif /* _ASM_X86_INTEL_RDT_COMMON_H */
diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c
index 7d7aebe..f8e35cf 100644
--- a/arch/x86/kernel/cpu/intel_rdt.c
+++ b/arch/x86/kernel/cpu/intel_rdt.c
@@ -27,16 +27,57 @@
#include <linux/slab.h>
#include <linux/err.h>
+#include <asm/intel_rdt_common.h>
+#include <asm/intel-family.h>
+#include <asm/intel_rdt.h>
+
+/*
+ * cache_alloc_hsw_probe() - Have to probe for Intel haswell server CPUs
+ * as they do not have CPUID enumeration support for Cache allocation.
+ * The check for Vendor/Family/Model is not enough to guarantee that
+ * the MSRs won't #GP fault because only the following SKUs support
+ * CAT:
+ * Intel(R) Xeon(R) CPU E5-2658 v3 @ 2.20GHz
+ * Intel(R) Xeon(R) CPU E5-2648L v3 @ 1.80GHz
+ * Intel(R) Xeon(R) CPU E5-2628L v3 @ 2.00GHz
+ * Intel(R) Xeon(R) CPU E5-2618L v3 @ 2.30GHz
+ * Intel(R) Xeon(R) CPU E5-2608L v3 @ 2.00GHz
+ * Intel(R) Xeon(R) CPU E5-2658A v3 @ 2.20GHz
+ *
+ * Probe by trying to write the first of the L3 cach mask registers
+ * and checking that the bits stick. Max CLOSids is always 4 and max cbm length
+ * is always 20 on hsw server parts. The minimum cache bitmask length
+ * allowed for HSW server is always 2 bits. Hardcode all of them.
+ */
+static inline bool cache_alloc_hsw_probe(void)
+{
+ if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
+ boot_cpu_data.x86 == 6 &&
+ boot_cpu_data.x86_model == INTEL_FAM6_HASWELL_X) {
+ u32 l, h, max_cbm = BIT_MASK(20) - 1;
+
+ if (wrmsr_safe(IA32_L3_CBM_BASE, max_cbm, 0))
+ return false;
+ rdmsr(IA32_L3_CBM_BASE, l, h);
+
+ /* If all the bits were set in MSR, return success */
+ return l == max_cbm;
+ }
+
+ return false;
+}
+
static inline bool get_rdt_resources(void)
{
- bool ret = false;
+ if (cache_alloc_hsw_probe())
+ return true;
if (!boot_cpu_has(X86_FEATURE_RDT_A))
return false;
- if (boot_cpu_has(X86_FEATURE_CAT_L3))
- ret = true;
+ if (!boot_cpu_has(X86_FEATURE_CAT_L3))
+ return false;
- return ret;
+ return true;
}
static int __init intel_rdt_late_init(void)
next prev parent reply other threads:[~2016-10-26 21:28 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-22 13:19 [PATCH v5 00/18] Intel Cache Allocation Technology Fenghua Yu
2016-10-22 13:19 ` [PATCH v5 01/18] Documentation, ABI: Add a document entry for cache id Fenghua Yu
2016-10-26 21:25 ` [tip:x86/cache] Documentation, ABI: Document the new sysfs files for cpu cache ids tip-bot for Tony Luck
2016-10-22 13:19 ` [PATCH v5 02/18] cacheinfo: Introduce cache id Fenghua Yu
2016-10-26 21:25 ` [tip:x86/cache] " tip-bot for Fenghua Yu
2016-10-22 13:19 ` [PATCH v5 03/18] x86/intel_cacheinfo: Enable cache id in cache info Fenghua Yu
2016-10-26 21:26 ` [tip:x86/cache] " tip-bot for Fenghua Yu
2016-10-22 13:19 ` [PATCH v5 04/18] x86/intel_rdt: Feature discovery Fenghua Yu
2016-10-26 14:15 ` Borislav Petkov
2016-10-26 14:28 ` Thomas Gleixner
2016-10-26 21:26 ` [tip:x86/cache] x86/cpufeature: Add RDT CPUID feature bits tip-bot for Fenghua Yu
2016-10-22 13:19 ` [PATCH v5 05/18] Documentation, x86: Documentation for Intel resource allocation user interface Fenghua Yu
2016-10-22 13:19 ` [PATCH v5 06/18] x86/intel_rdt: Add CONFIG, Makefile, and basic initialization Fenghua Yu
2016-10-26 20:43 ` Thomas Gleixner
2016-10-26 21:27 ` [tip:x86/cache] " tip-bot for Fenghua Yu
2016-10-22 13:19 ` [PATCH v5 07/18] x86/intel_rdt: Add Haswell feature discovery Fenghua Yu
2016-10-26 21:27 ` tip-bot for Fenghua Yu [this message]
2016-10-22 13:19 ` [PATCH v5 08/18] x86/intel_rdt: Pick up L3/L2 RDT parameters from CPUID Fenghua Yu
2016-10-26 21:28 ` [tip:x86/cache] " tip-bot for Fenghua Yu
2016-10-22 13:19 ` [PATCH v5 09/18] x86/cqm: Move PQR_ASSOC management code into generic code used by both CQM and CAT Fenghua Yu
2016-10-26 21:29 ` [tip:x86/cache] x86/cqm: Share PQR_ASSOC related data between " tip-bot for Fenghua Yu
2016-10-22 13:19 ` [PATCH v5 10/18] x86/intel_rdt: Build structures for each resource based on cache topology Fenghua Yu
2016-10-26 13:02 ` Thomas Gleixner
2016-10-26 16:06 ` Luck, Tony
2016-10-26 17:31 ` Thomas Gleixner
2016-10-26 21:14 ` Fenghua Yu
2016-10-26 21:18 ` Thomas Gleixner
2016-10-22 13:19 ` [PATCH v5 11/18] x86/intel_rdt: Add basic resctrl filesystem support Fenghua Yu
2016-10-26 13:52 ` Thomas Gleixner
2016-10-22 13:19 ` [PATCH v5 12/18] x86/intel_rdt: Add "info" files to resctrl file system Fenghua Yu
2016-10-26 14:45 ` Thomas Gleixner
2016-10-26 15:48 ` Luck, Tony
2016-10-26 17:33 ` Thomas Gleixner
2016-10-27 18:17 ` Fenghua Yu
2016-10-27 18:25 ` Thomas Gleixner
2016-10-27 18:35 ` Fenghua Yu
2016-10-22 13:20 ` [PATCH v5 13/18] x86/intel_rdt: Add mkdir " Fenghua Yu
2016-10-26 15:01 ` Thomas Gleixner
2016-10-28 17:51 ` Fenghua Yu
2016-10-28 18:41 ` Thomas Gleixner
2016-10-22 13:20 ` [PATCH v5 14/18] x86/intel_rdt: Add cpus file Fenghua Yu
2016-10-26 17:57 ` Thomas Gleixner
2016-10-22 13:20 ` [PATCH v5 15/18] x86/intel_rdt: Add tasks files Fenghua Yu
2016-10-26 15:27 ` Thomas Gleixner
2016-10-22 13:20 ` [PATCH v5 16/18] x86/intel_rdt: Add schemata file Fenghua Yu
2016-10-22 13:20 ` [PATCH v5 17/18] x86/intel_rdt: Add scheduler hook Fenghua Yu
2016-10-22 13:20 ` [PATCH v5 18/18] MAINTAINERS: Add maintainer for Intel RDT resource allocation Fenghua Yu
2016-10-26 21:39 ` [PATCH v5 00/18] Intel Cache Allocation Technology Thomas Gleixner
2016-10-26 21:54 ` Fenghua Yu
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