From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1424712AbcFHLDN (ORCPT ); Wed, 8 Jun 2016 07:03:13 -0400 Received: from terminus.zytor.com ([198.137.202.10]:57832 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932121AbcFHLDJ (ORCPT ); Wed, 8 Jun 2016 07:03:09 -0400 Date: Wed, 8 Jun 2016 04:01:54 -0700 From: tip-bot for Dave Hansen Message-ID: Cc: alexander.shishkin@linux.intel.com, dave@sr71.net, torvalds@linux-foundation.org, mingo@kernel.org, acme@redhat.com, luto@kernel.org, tglx@linutronix.de, luto@amacapital.net, eranian@google.com, bp@alien8.de, hpa@zytor.com, jolsa@redhat.com, dave.hansen@linux.intel.com, dvlasenk@redhat.com, peterz@infradead.org, vincent.weaver@maine.edu, brgerst@gmail.com, linux-kernel@vger.kernel.org Reply-To: dave.hansen@linux.intel.com, hpa@zytor.com, jolsa@redhat.com, bp@alien8.de, vincent.weaver@maine.edu, brgerst@gmail.com, linux-kernel@vger.kernel.org, peterz@infradead.org, dvlasenk@redhat.com, alexander.shishkin@linux.intel.com, dave@sr71.net, torvalds@linux-foundation.org, mingo@kernel.org, luto@amacapital.net, eranian@google.com, tglx@linutronix.de, luto@kernel.org, acme@redhat.com In-Reply-To: <20160603001933.99A402B0@viggo.jf.intel.com> References: <20160603001933.99A402B0@viggo.jf.intel.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:perf/core] perf/x86/msr: Use Intel family macros for MSR events code Git-Commit-ID: 353bf605a771e3c86b21de017e9525aba7d64770 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: 353bf605a771e3c86b21de017e9525aba7d64770 Gitweb: http://git.kernel.org/tip/353bf605a771e3c86b21de017e9525aba7d64770 Author: Dave Hansen AuthorDate: Thu, 2 Jun 2016 17:19:33 -0700 Committer: Ingo Molnar CommitDate: Wed, 8 Jun 2016 12:05:59 +0200 perf/x86/msr: Use Intel family macros for MSR events code Use the new INTEL_MODEL_* macros for arch/x86/events/msr.c. This code appears to be missing handling for "WESTMERE2" and "SKYLAKE_X". Signed-off-by: Dave Hansen Cc: Alexander Shishkin Cc: Andy Lutomirski Cc: Andy Lutomirski Cc: Arnaldo Carvalho de Melo Cc: Borislav Petkov Cc: Brian Gerst Cc: Dave Hansen Cc: Denys Vlasenko Cc: H. Peter Anvin Cc: Jiri Olsa Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Thomas Gleixner Cc: Vince Weaver Cc: jacob.jun.pan@intel.com Link: http://lkml.kernel.org/r/20160603001933.99A402B0@viggo.jf.intel.com Signed-off-by: Ingo Molnar --- arch/x86/events/msr.c | 47 ++++++++++++++++++++++++----------------------- 1 file changed, 24 insertions(+), 23 deletions(-) diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c index 85ef3c2..83cf13e 100644 --- a/arch/x86/events/msr.c +++ b/arch/x86/events/msr.c @@ -1,4 +1,5 @@ #include +#include enum perf_msr_id { PERF_MSR_TSC = 0, @@ -34,39 +35,39 @@ static bool test_intel(int idx) return false; switch (boot_cpu_data.x86_model) { - case 30: /* 45nm Nehalem */ - case 26: /* 45nm Nehalem-EP */ - case 46: /* 45nm Nehalem-EX */ + case INTEL_FAM6_NEHALEM: + case INTEL_FAM6_NEHALEM_EP: + case INTEL_FAM6_NEHALEM_EX: - case 37: /* 32nm Westmere */ - case 44: /* 32nm Westmere-EP */ - case 47: /* 32nm Westmere-EX */ + case INTEL_FAM6_WESTMERE: + case INTEL_FAM6_WESTMERE_EP: + case INTEL_FAM6_WESTMERE_EX: - case 42: /* 32nm SandyBridge */ - case 45: /* 32nm SandyBridge-E/EN/EP */ + case INTEL_FAM6_SANDYBRIDGE: + case INTEL_FAM6_SANDYBRIDGE_X: - case 58: /* 22nm IvyBridge */ - case 62: /* 22nm IvyBridge-EP/EX */ + case INTEL_FAM6_IVYBRIDGE: + case INTEL_FAM6_IVYBRIDGE_X: - case 60: /* 22nm Haswell Core */ - case 63: /* 22nm Haswell Server */ - case 69: /* 22nm Haswell ULT */ - case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */ + case INTEL_FAM6_HASWELL_CORE: + case INTEL_FAM6_HASWELL_X: + case INTEL_FAM6_HASWELL_ULT: + case INTEL_FAM6_HASWELL_GT3E: - case 61: /* 14nm Broadwell Core-M */ - case 86: /* 14nm Broadwell Xeon D */ - case 71: /* 14nm Broadwell + GT3e (Intel Iris Pro graphics) */ - case 79: /* 14nm Broadwell Server */ + case INTEL_FAM6_BROADWELL_CORE: + case INTEL_FAM6_BROADWELL_XEON_D: + case INTEL_FAM6_BROADWELL_GT3E: + case INTEL_FAM6_BROADWELL_X: - case 55: /* 22nm Atom "Silvermont" */ - case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */ - case 76: /* 14nm Atom "Airmont" */ + case INTEL_FAM6_ATOM_SILVERMONT1: + case INTEL_FAM6_ATOM_SILVERMONT2: + case INTEL_FAM6_ATOM_AIRMONT: if (idx == PERF_MSR_SMI) return true; break; - case 78: /* 14nm Skylake Mobile */ - case 94: /* 14nm Skylake Desktop */ + case INTEL_FAM6_SKYLAKE_MOBILE: + case INTEL_FAM6_SKYLAKE_DESKTOP: if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF) return true; break;