From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752014AbcF0M4T (ORCPT ); Mon, 27 Jun 2016 08:56:19 -0400 Received: from terminus.zytor.com ([198.137.202.10]:41584 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751852AbcF0M4Q (ORCPT ); Mon, 27 Jun 2016 08:56:16 -0400 Date: Mon, 27 Jun 2016 05:55:37 -0700 From: tip-bot for David Carrillo-Cisneros Message-ID: Cc: linux-kernel@vger.kernel.org, acme@redhat.com, kan.liang@intel.com, peterz@infradead.org, eranian@google.com, ak@linux.intel.com, torvalds@linux-foundation.org, vincent.weaver@maine.edu, davidcc@google.com, tglx@linutronix.de, jolsa@redhat.com, mingo@kernel.org, hpa@zytor.com, alexander.shishkin@linux.intel.com Reply-To: jolsa@redhat.com, tglx@linutronix.de, davidcc@google.com, vincent.weaver@maine.edu, mingo@kernel.org, hpa@zytor.com, alexander.shishkin@linux.intel.com, linux-kernel@vger.kernel.org, acme@redhat.com, eranian@google.com, kan.liang@intel.com, peterz@infradead.org, torvalds@linux-foundation.org, ak@linux.intel.com In-Reply-To: <1466533874-52003-5-git-send-email-davidcc@google.com> References: <1466533874-52003-5-git-send-email-davidcc@google.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:perf/core] perf/x86/intel: Add MSR_LAST_BRANCH_FROM_x quirk for ctx switch Git-Commit-ID: 71adae99ed187de9fcf988cc8873ee2c3af3385f X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: 71adae99ed187de9fcf988cc8873ee2c3af3385f Gitweb: http://git.kernel.org/tip/71adae99ed187de9fcf988cc8873ee2c3af3385f Author: David Carrillo-Cisneros AuthorDate: Tue, 21 Jun 2016 11:31:13 -0700 Committer: Ingo Molnar CommitDate: Mon, 27 Jun 2016 11:34:20 +0200 perf/x86/intel: Add MSR_LAST_BRANCH_FROM_x quirk for ctx switch Add quirk for context switch to save/restore the value of MSR_LAST_BRANCH_FROM_x when LBR is enabled and there is potential for kernel addresses to be in the lbr_from register. To test this patch, use a perf tool and kernel with the patch next in this series. That patch removes the work around that masked the hw bug: $ ./lbr_perf record --call-graph lbr -e cycles:k sleep 1 where lbr_perf is the patched perf tool, that allows to specify :k on lbr mode. The above command will trigger a #GPF : WARNING: CPU: 28 PID: 14096 at arch/x86/mm/extable.c:65 ex_handler_wrmsr_unsafe+0x70/0x80 unchecked MSR access error: WRMSR to 0x681 (tried to write 0x1fffffff81010794) ... Call Trace: [] dump_stack+0x4d/0x63 [] __warn+0xe5/0x100 [] warn_slowpath_fmt+0x49/0x50 [] ex_handler_wrmsr_unsafe+0x70/0x80 [] fixup_exception+0x42/0x50 [] do_general_protection+0x8a/0x160 [] general_protection+0x22/0x30 [] ? intel_pmu_lbr_sched_task+0xc9/0x380 [] intel_pmu_sched_task+0x3c/0x60 [] x86_pmu_sched_task+0x1b/0x20 [] perf_pmu_sched_task+0x6b/0xb0 [] __perf_event_task_sched_in+0x7d/0x150 [] finish_task_switch+0x15c/0x200 [] __schedule+0x274/0x6cc [] schedule+0x39/0x90 [] exit_to_usermode_loop+0x39/0x89 [] prepare_exit_to_usermode+0x2e/0x30 [] retint_user+0x8/0x10 Signed-off-by: David Carrillo-Cisneros Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Stephane Eranian Reviewed-by: Andi Kleen Cc: Alexander Shishkin Cc: Arnaldo Carvalho de Melo Cc: Jiri Olsa Cc: Kan Liang Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: Vince Weaver Link: http://lkml.kernel.org/r/1466533874-52003-5-git-send-email-davidcc@google.com Signed-off-by: Ingo Molnar --- arch/x86/events/intel/lbr.c | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c index 0da0eb0..52bef15 100644 --- a/arch/x86/events/intel/lbr.c +++ b/arch/x86/events/intel/lbr.c @@ -284,6 +284,20 @@ inline u64 lbr_from_signext_quirk_wr(u64 val) return val; } +/* + * If quirk is needed, ensure sign extension is 61 bits: + */ +u64 lbr_from_signext_quirk_rd(u64 val) +{ + if (static_branch_unlikely(&lbr_from_quirk_key)) + /* + * Quirk is on when TSX is not enabled. Therefore TSX + * flags must be read as OFF. + */ + val &= ~(LBR_FROM_FLAG_IN_TX | LBR_FROM_FLAG_ABORT); + return val; +} + static void __intel_pmu_lbr_restore(struct x86_perf_task_context *task_ctx) { int i; @@ -300,7 +314,8 @@ static void __intel_pmu_lbr_restore(struct x86_perf_task_context *task_ctx) tos = task_ctx->tos; for (i = 0; i < tos; i++) { lbr_idx = (tos - i) & mask; - wrmsrl(x86_pmu.lbr_from + lbr_idx, task_ctx->lbr_from[i]); + wrmsrl(x86_pmu.lbr_from + lbr_idx, + lbr_from_signext_quirk_wr(task_ctx->lbr_from[i])); wrmsrl(x86_pmu.lbr_to + lbr_idx, task_ctx->lbr_to[i]); if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO) wrmsrl(MSR_LBR_INFO_0 + lbr_idx, task_ctx->lbr_info[i]); @@ -313,7 +328,7 @@ static void __intel_pmu_lbr_save(struct x86_perf_task_context *task_ctx) { int i; unsigned lbr_idx, mask; - u64 tos; + u64 tos, val; if (task_ctx->lbr_callstack_users == 0) { task_ctx->lbr_stack_state = LBR_NONE; @@ -324,7 +339,8 @@ static void __intel_pmu_lbr_save(struct x86_perf_task_context *task_ctx) tos = intel_pmu_lbr_tos(); for (i = 0; i < tos; i++) { lbr_idx = (tos - i) & mask; - rdmsrl(x86_pmu.lbr_from + lbr_idx, task_ctx->lbr_from[i]); + rdmsrl(x86_pmu.lbr_from + lbr_idx, val); + task_ctx->lbr_from[i] = lbr_from_signext_quirk_rd(val); rdmsrl(x86_pmu.lbr_to + lbr_idx, task_ctx->lbr_to[i]); if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO) rdmsrl(MSR_LBR_INFO_0 + lbr_idx, task_ctx->lbr_info[i]); @@ -502,6 +518,8 @@ static void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc) int lbr_flags = lbr_desc[lbr_format]; rdmsrl(x86_pmu.lbr_from + lbr_idx, from); + from = lbr_from_signext_quirk_rd(from); + rdmsrl(x86_pmu.lbr_to + lbr_idx, to); if (lbr_format == LBR_FORMAT_INFO && need_info) {