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From: tip-bot for Yazen Ghannam <tipbot@zytor.com>
To: linux-tip-commits@vger.kernel.org
Cc: dvlasenk@redhat.com, bp@alien8.de, mingo@kernel.org,
	tony.luck@intel.com, brgerst@gmail.com, Yazen.Ghannam@amd.com,
	hpa@zytor.com, linux-edac@vger.kernel.org, luto@amacapital.net,
	tglx@linutronix.de, linux-kernel@vger.kernel.org, bp@suse.de,
	peterz@infradead.org, torvalds@linux-foundation.org
Subject: [tip:ras/core] x86/cpu: Add detection of AMD RAS Capabilities
Date: Thu, 12 May 2016 03:27:57 -0700
Message-ID: <tip-71faad43060d3d2040583635fbf7d1bdb3d04118@git.kernel.org> (raw)
In-Reply-To: <1462971509-3856-5-git-send-email-bp@alien8.de>

Commit-ID:  71faad43060d3d2040583635fbf7d1bdb3d04118
Gitweb:     http://git.kernel.org/tip/71faad43060d3d2040583635fbf7d1bdb3d04118
Author:     Yazen Ghannam <Yazen.Ghannam@amd.com>
AuthorDate: Wed, 11 May 2016 14:58:26 +0200
Committer:  Ingo Molnar <mingo@kernel.org>
CommitDate: Thu, 12 May 2016 09:08:22 +0200

x86/cpu: Add detection of AMD RAS Capabilities

Add a new CPUID leaf to hold the contents of CPUID 0x80000007_EBX (RasCap).

Define bits that are currently in use:

 Bit 0: McaOverflowRecov
 Bit 1: SUCCOR
 Bit 3: ScalableMca

Signed-off-by: Yazen Ghannam <Yazen.Ghannam@amd.com>
[ Shorten comment. ]
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1462971509-3856-5-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
 arch/x86/include/asm/cpufeature.h  |  1 +
 arch/x86/include/asm/cpufeatures.h |  7 ++++++-
 arch/x86/kernel/cpu/common.c       | 10 +++++++---
 3 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 3636ec0..53ac9bb 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -27,6 +27,7 @@ enum cpuid_leafs
 	CPUID_6_EAX,
 	CPUID_8000_000A_EDX,
 	CPUID_7_ECX,
+	CPUID_8000_0007_EBX,
 };
 
 #ifdef CONFIG_X86_FEATURE_NAMES
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 8f9afef..d4e5018 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -12,7 +12,7 @@
 /*
  * Defines x86 CPU feature bits
  */
-#define NCAPINTS	17	/* N 32-bit words worth of info */
+#define NCAPINTS	18	/* N 32-bit words worth of info */
 #define NBUGINTS	1	/* N 32-bit bug flags */
 
 /*
@@ -280,6 +280,11 @@
 #define X86_FEATURE_PKU		(16*32+ 3) /* Protection Keys for Userspace */
 #define X86_FEATURE_OSPKE	(16*32+ 4) /* OS Protection Keys Enable */
 
+/* AMD-defined CPU features, CPUID level 0x80000007 (ebx), word 17 */
+#define X86_FEATURE_OVERFLOW_RECOV (17*32+0) /* MCA overflow recovery support */
+#define X86_FEATURE_SUCCOR	(17*32+1) /* Uncorrectable error containment and recovery */
+#define X86_FEATURE_SMCA	(17*32+3) /* Scalable MCA */
+
 /*
  * BUG word(s)
  */
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 8394b3d..dbc6f06 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -717,6 +717,13 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
 		}
 	}
 
+	if (c->extended_cpuid_level >= 0x80000007) {
+		cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
+
+		c->x86_capability[CPUID_8000_0007_EBX] = ebx;
+		c->x86_power = edx;
+	}
+
 	if (c->extended_cpuid_level >= 0x80000008) {
 		cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
 
@@ -729,9 +736,6 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
 		c->x86_phys_bits = 36;
 #endif
 
-	if (c->extended_cpuid_level >= 0x80000007)
-		c->x86_power = cpuid_edx(0x80000007);
-
 	if (c->extended_cpuid_level >= 0x8000000a)
 		c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
 

  reply index

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-05-11 12:58 [PATCH 0/7] x86/ras: RAS queue Borislav Petkov
2016-05-11 12:58 ` [PATCH 1/7] x86/mce/AMD: Log Deferred Errors using SMCA MCA_DE{STAT,ADDR} registers Borislav Petkov
2016-05-12 10:26   ` [tip:ras/core] " tip-bot for Yazen Ghannam
2016-05-11 12:58 ` [PATCH 2/7] x86/mce/AMD: Disable LogDeferredInMcaStat for SMCA systems Borislav Petkov
2016-05-12 10:27   ` [tip:ras/core] " tip-bot for Yazen Ghannam
2016-05-11 12:58 ` [PATCH 3/7] x86/mce/AMD: Save an indentation level in prepare_threshold_block() Borislav Petkov
2016-05-12 10:27   ` [tip:ras/core] " tip-bot for Borislav Petkov
2016-05-11 12:58 ` [PATCH 4/7] x86/cpu: Add detection of AMD RAS Capabilities Borislav Petkov
2016-05-12 10:27   ` tip-bot for Yazen Ghannam [this message]
2016-05-11 12:58 ` [PATCH 5/7] x86/mce: Update AMD mcheck init to use cpu_has() facilities Borislav Petkov
2016-05-12 10:28   ` [tip:ras/core] " tip-bot for Yazen Ghannam
2016-05-11 12:58 ` [PATCH 6/7] EDAC, mce_amd: Detect SMCA using X86_FEATURE_SMCA Borislav Petkov
2016-05-12 10:28   ` [tip:ras/core] " tip-bot for Yazen Ghannam
2016-05-11 12:58 ` [PATCH 7/7] x86/RAS: Add SMCA support to AMD Error Injector Borislav Petkov
2016-05-12 10:29   ` [tip:ras/core] " tip-bot for Yazen Ghannam

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