From mboxrd@z Thu Jan 1 00:00:00 1970 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755305AbeAIAyw (ORCPT + 1 other); Mon, 8 Jan 2018 19:54:52 -0500 Received: from terminus.zytor.com ([65.50.211.136]:54583 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755137AbeAIAyt (ORCPT ); Mon, 8 Jan 2018 19:54:49 -0500 Date: Mon, 8 Jan 2018 16:49:16 -0800 From: tip-bot for Tom Lendacky Message-ID: Cc: dwmw@amazon.co.uk, tglx@linutronix.de, bp@suse.de, pjt@google.com, thomas.lendacky@amd.com, gregkh@linux-foundation.org, peterz@infradead.org, tim.c.chen@linux.intel.com, dave.hansen@intel.com, linux-kernel@vger.kernel.org, dan.j.williams@intel.com, torvalds@linux-foundation.org, bp@alien8.de, mingo@kernel.org, hpa@zytor.com Reply-To: linux-kernel@vger.kernel.org, dave.hansen@intel.com, mingo@kernel.org, hpa@zytor.com, bp@alien8.de, torvalds@linux-foundation.org, dan.j.williams@intel.com, tglx@linutronix.de, dwmw@amazon.co.uk, tim.c.chen@linux.intel.com, peterz@infradead.org, thomas.lendacky@amd.com, gregkh@linux-foundation.org, pjt@google.com, bp@suse.de In-Reply-To: <20180108220932.12580.52458.stgit@tlendack-t1.amdoffice.net> References: <20180108220932.12580.52458.stgit@tlendack-t1.amdoffice.net> To: linux-tip-commits@vger.kernel.org Subject: [tip:x86/pti] x86/cpu/AMD: Use LFENCE_RDTSC in preference to MFENCE_RDTSC Git-Commit-ID: 9c6a73c75864ad9fa49e5fa6513e4c4071c0e29f X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: Commit-ID: 9c6a73c75864ad9fa49e5fa6513e4c4071c0e29f Gitweb: https://git.kernel.org/tip/9c6a73c75864ad9fa49e5fa6513e4c4071c0e29f Author: Tom Lendacky AuthorDate: Mon, 8 Jan 2018 16:09:32 -0600 Committer: Thomas Gleixner CommitDate: Tue, 9 Jan 2018 01:43:11 +0100 x86/cpu/AMD: Use LFENCE_RDTSC in preference to MFENCE_RDTSC With LFENCE now a serializing instruction, use LFENCE_RDTSC in preference to MFENCE_RDTSC. However, since the kernel could be running under a hypervisor that does not support writing that MSR, read the MSR back and verify that the bit has been set successfully. If the MSR can be read and the bit is set, then set the LFENCE_RDTSC feature, otherwise set the MFENCE_RDTSC feature. Signed-off-by: Tom Lendacky Signed-off-by: Thomas Gleixner Reviewed-by: Reviewed-by: Borislav Petkov Cc: Peter Zijlstra Cc: Tim Chen Cc: Dave Hansen Cc: Borislav Petkov Cc: Dan Williams Cc: Linus Torvalds Cc: Greg Kroah-Hartman Cc: David Woodhouse Cc: Paul Turner Link: https://lkml.kernel.org/r/20180108220932.12580.52458.stgit@tlendack-t1.amdoffice.net --- arch/x86/include/asm/msr-index.h | 1 + arch/x86/kernel/cpu/amd.c | 18 ++++++++++++++++-- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 1e7d710..fa11fb1 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -354,6 +354,7 @@ #define MSR_FAM10H_NODE_ID 0xc001100c #define MSR_F10H_DECFG 0xc0011029 #define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1 +#define MSR_F10H_DECFG_LFENCE_SERIALIZE BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT) /* K8 MSRs */ #define MSR_K8_TOP_MEM1 0xc001001a diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 5b438d8..ea831c8 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -829,6 +829,9 @@ static void init_amd(struct cpuinfo_x86 *c) set_cpu_cap(c, X86_FEATURE_K8); if (cpu_has(c, X86_FEATURE_XMM2)) { + unsigned long long val; + int ret; + /* * A serializing LFENCE has less overhead than MFENCE, so * use it for execution serialization. On families which @@ -839,8 +842,19 @@ static void init_amd(struct cpuinfo_x86 *c) msr_set_bit(MSR_F10H_DECFG, MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT); - /* MFENCE stops RDTSC speculation */ - set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); + /* + * Verify that the MSR write was successful (could be running + * under a hypervisor) and only then assume that LFENCE is + * serializing. + */ + ret = rdmsrl_safe(MSR_F10H_DECFG, &val); + if (!ret && (val & MSR_F10H_DECFG_LFENCE_SERIALIZE)) { + /* A serializing LFENCE stops RDTSC speculation */ + set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); + } else { + /* MFENCE stops RDTSC speculation */ + set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); + } } /*