From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752895AbdDNIuw (ORCPT ); Fri, 14 Apr 2017 04:50:52 -0400 Received: from terminus.zytor.com ([65.50.211.136]:46267 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752046AbdDNIut (ORCPT ); Fri, 14 Apr 2017 04:50:49 -0400 Date: Fri, 14 Apr 2017 01:49:35 -0700 From: tip-bot for Piotr Luc Message-ID: Cc: bp@suse.de, linux-edac@vger.kernel.org, piotr.luc@intel.com, linux-kernel@vger.kernel.org, tglx@linutronix.de, hpa@zytor.com, mingo@kernel.org, tony.luck@intel.com Reply-To: hpa@zytor.com, tglx@linutronix.de, mingo@kernel.org, tony.luck@intel.com, linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org, piotr.luc@intel.com, bp@suse.de In-Reply-To: <20170413201056.10525-1-bp@alien8.de> References: <20170408172004.8463-1-piotr.luc@intel.com> <20170413201056.10525-1-bp@alien8.de> To: linux-tip-commits@vger.kernel.org Subject: [tip:ras/core] x86/mce: Enable PPIN for Knights Landing/Mill Git-Commit-ID: 9ea74f7c70cd5e408f1cfbda0e6836929f820d49 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: 9ea74f7c70cd5e408f1cfbda0e6836929f820d49 Gitweb: http://git.kernel.org/tip/9ea74f7c70cd5e408f1cfbda0e6836929f820d49 Author: Piotr Luc AuthorDate: Thu, 13 Apr 2017 22:10:56 +0200 Committer: Thomas Gleixner CommitDate: Fri, 14 Apr 2017 10:46:12 +0200 x86/mce: Enable PPIN for Knights Landing/Mill Intel Xeon Phi processors (KNL and KNM) support PPIN as well, so add their CPUIDs to the whitelist of supported processors. Signed-off-by: Piotr Luc Signed-off-by: Borislav Petkov Cc: Tony Luck Cc: linux-edac Link: http://lkml.kernel.org/r/20170408172004.8463-1-piotr.luc@intel.com Link: http://lkml.kernel.org/r/20170413201056.10525-1-bp@alien8.de Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/mcheck/mce_intel.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c index 190b3e6..e84db79 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_intel.c +++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c @@ -481,6 +481,9 @@ static void intel_ppin_init(struct cpuinfo_x86 *c) case INTEL_FAM6_BROADWELL_XEON_D: case INTEL_FAM6_BROADWELL_X: case INTEL_FAM6_SKYLAKE_X: + case INTEL_FAM6_XEON_PHI_KNL: + case INTEL_FAM6_XEON_PHI_KNM: + if (rdmsrl_safe(MSR_PPIN_CTL, &val)) return;