From: tip-bot for Jacob Shin <jacob.shin@amd.com>
To: linux-tip-commits@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, paulus@samba.org,
eranian@google.com, hpa@zytor.com, mingo@kernel.org,
a.p.zijlstra@chello.nl, acme@ghostprotocols.net,
jolsa@redhat.com, jacob.shin@amd.com, tglx@linutronix.de
Subject: [tip:perf/core] perf/x86/amd: Use proper naming scheme for AMD bit field definitions
Date: Wed, 6 Feb 2013 12:30:30 -0800 [thread overview]
Message-ID: <tip-9f19010af8c651879ac2c36f1a808a3a4419cd40@git.kernel.org> (raw)
In-Reply-To: <1360171589-6381-4-git-send-email-jacob.shin@amd.com>
Commit-ID: 9f19010af8c651879ac2c36f1a808a3a4419cd40
Gitweb: http://git.kernel.org/tip/9f19010af8c651879ac2c36f1a808a3a4419cd40
Author: Jacob Shin <jacob.shin@amd.com>
AuthorDate: Wed, 6 Feb 2013 11:26:26 -0600
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Wed, 6 Feb 2013 19:45:23 +0100
perf/x86/amd: Use proper naming scheme for AMD bit field definitions
Update these AMD bit field names to be consistent with naming
convention followed by the rest of the file.
Signed-off-by: Jacob Shin <jacob.shin@amd.com>
Acked-by: Stephane Eranian <eranian@google.com>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/1360171589-6381-4-git-send-email-jacob.shin@amd.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/include/asm/perf_event.h | 4 ++--
arch/x86/kernel/cpu/perf_event_amd.c | 8 ++++----
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 4fabcdf..2234eaaec 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -29,8 +29,8 @@
#define ARCH_PERFMON_EVENTSEL_INV (1ULL << 23)
#define ARCH_PERFMON_EVENTSEL_CMASK 0xFF000000ULL
-#define AMD_PERFMON_EVENTSEL_GUESTONLY (1ULL << 40)
-#define AMD_PERFMON_EVENTSEL_HOSTONLY (1ULL << 41)
+#define AMD64_EVENTSEL_GUESTONLY (1ULL << 40)
+#define AMD64_EVENTSEL_HOSTONLY (1ULL << 41)
#define AMD64_EVENTSEL_EVENT \
(ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c
index f8c9dfb..aea8c20 100644
--- a/arch/x86/kernel/cpu/perf_event_amd.c
+++ b/arch/x86/kernel/cpu/perf_event_amd.c
@@ -156,9 +156,9 @@ static int amd_pmu_hw_config(struct perf_event *event)
event->hw.config &= ~(ARCH_PERFMON_EVENTSEL_USR |
ARCH_PERFMON_EVENTSEL_OS);
else if (event->attr.exclude_host)
- event->hw.config |= AMD_PERFMON_EVENTSEL_GUESTONLY;
+ event->hw.config |= AMD64_EVENTSEL_GUESTONLY;
else if (event->attr.exclude_guest)
- event->hw.config |= AMD_PERFMON_EVENTSEL_HOSTONLY;
+ event->hw.config |= AMD64_EVENTSEL_HOSTONLY;
if (event->attr.type != PERF_TYPE_RAW)
return 0;
@@ -336,7 +336,7 @@ static void amd_pmu_cpu_starting(int cpu)
struct amd_nb *nb;
int i, nb_id;
- cpuc->perf_ctr_virt_mask = AMD_PERFMON_EVENTSEL_HOSTONLY;
+ cpuc->perf_ctr_virt_mask = AMD64_EVENTSEL_HOSTONLY;
if (boot_cpu_data.x86_max_cores < 2)
return;
@@ -669,7 +669,7 @@ void amd_pmu_disable_virt(void)
* SVM is disabled the Guest-only bits still gets set and the counter
* will not count anything.
*/
- cpuc->perf_ctr_virt_mask = AMD_PERFMON_EVENTSEL_HOSTONLY;
+ cpuc->perf_ctr_virt_mask = AMD64_EVENTSEL_HOSTONLY;
/* Reload all events */
x86_pmu_disable_all();
next prev parent reply other threads:[~2013-02-06 20:31 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-02-06 17:26 [PATCH V6 0/6] perf, amd: Enable AMD family 15h northbridge counters Jacob Shin
2013-02-06 17:26 ` [PATCH 1/6] perf, amd: Rework northbridge event constraints handler Jacob Shin
2013-02-06 20:28 ` [tip:perf/core] perf/x86/amd: " tip-bot for Robert Richter
2013-02-06 17:26 ` [PATCH 2/6] perf, amd: Generalize northbridge constraints code for family 15h Jacob Shin
2013-02-06 20:29 ` [tip:perf/core] perf/x86/amd: " tip-bot for Robert Richter
2013-02-06 17:26 ` [PATCH 3/6] perf, amd: Use proper naming scheme for AMD bit field definitions Jacob Shin
2013-02-06 20:30 ` tip-bot for Jacob Shin [this message]
2013-02-06 17:26 ` [PATCH 4/6] perf, x86: Move MSR address offset calculation to architecture specific files Jacob Shin
2013-02-06 20:31 ` [tip:perf/core] perf/x86: " tip-bot for Jacob Shin
2013-02-06 17:26 ` [PATCH 5/6] perf, x86: Allow for architecture specific RDPMC indexes Jacob Shin
2013-02-06 20:32 ` [tip:perf/core] perf/x86: " tip-bot for Jacob Shin
2013-02-06 17:26 ` [PATCH 6/6] perf, amd: Enable northbridge performance counters on AMD family 15h Jacob Shin
2013-02-07 17:57 ` Jacob Shin
2013-02-07 17:58 ` Stephane Eranian
2013-02-07 19:09 ` Ingo Molnar
2013-02-08 11:16 ` Stephane Eranian
2013-02-11 16:26 ` Jacob Shin
2013-02-15 20:51 ` Jacob Shin
2013-02-18 8:30 ` [tip:perf/core] perf/x86/amd: " tip-bot for Jacob Shin
2013-02-06 17:31 ` [PATCH V6 0/6] perf, amd: Enable AMD family 15h northbridge counters Jacob Shin
2013-02-08 10:55 ` Stephane Eranian
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