From: tip-bot for Fenghua Yu <tipbot@zytor.com>
To: linux-tip-commits@vger.kernel.org
Cc: tglx@linutronix.de, dvlasenk@redhat.com, fenghua.yu@intel.com,
ashok.raj@intel.com, peterz@infradead.org, bp@alien8.de,
ravi.v.shankar@intel.com, mingo@kernel.org,
linux-kernel@vger.kernel.org, brgerst@gmail.com,
torvalds@linux-foundation.org, hpa@zytor.com,
luto@amacapital.net
Subject: [tip:x86/urgent] x86/cpufeatures: Enumerate MOVDIR64B instruction
Date: Wed, 24 Oct 2018 22:46:33 -0700 [thread overview]
Message-ID: <tip-ace6485a03266cc3c198ce8e927a1ce0ce139699@git.kernel.org> (raw)
In-Reply-To: <1540418237-125817-3-git-send-email-fenghua.yu@intel.com>
Commit-ID: ace6485a03266cc3c198ce8e927a1ce0ce139699
Gitweb: https://git.kernel.org/tip/ace6485a03266cc3c198ce8e927a1ce0ce139699
Author: Fenghua Yu <fenghua.yu@intel.com>
AuthorDate: Wed, 24 Oct 2018 14:57:17 -0700
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Thu, 25 Oct 2018 07:42:48 +0200
x86/cpufeatures: Enumerate MOVDIR64B instruction
MOVDIR64B moves 64-bytes as direct-store with 64-bytes write atomicity.
Direct store is implemented by using write combining (WC) for writing
data directly into memory without caching the data.
In low latency offload (e.g. Non-Volatile Memory, etc), MOVDIR64B writes
work descriptors (and data in some cases) to device-hosted work-queues
atomically without cache pollution.
Availability of the MOVDIR64B instruction is indicated by the
presence of the CPUID feature flag MOVDIR64B (CPUID.0x07.0x0:ECX[bit 28]).
Please check the latest Intel Architecture Instruction Set Extensions
and Future Features Programming Reference for more details on the CPUID
feature MOVDIR64B flag.
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Ashok Raj <ashok.raj@intel.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ravi V Shankar <ravi.v.shankar@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1540418237-125817-3-git-send-email-fenghua.yu@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/include/asm/cpufeatures.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 90934ee7b79a..28c4a502b419 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -332,6 +332,7 @@
#define X86_FEATURE_RDPID (16*32+22) /* RDPID instruction */
#define X86_FEATURE_CLDEMOTE (16*32+25) /* CLDEMOTE instruction */
#define X86_FEATURE_MOVDIRI (16*32+27) /* MOVDIRI instruction */
+#define X86_FEATURE_MOVDIR64B (16*32+28) /* MOVDIR64B instruction */
/* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */
#define X86_FEATURE_OVERFLOW_RECOV (17*32+ 0) /* MCA overflow recovery support */
prev parent reply other threads:[~2018-10-25 5:47 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-24 21:57 [PATCH 0/2] x86: Enumerate direct stores instructions Fenghua Yu
2018-10-24 21:57 ` [PATCH 1/2] x86/cpufeatures: Enumerate MOVDIRI instruction Fenghua Yu
2018-10-25 5:45 ` [tip:x86/urgent] " tip-bot for Fenghua Yu
2018-10-24 21:57 ` [PATCH 2/2] x86/cpufeatures: Enumerate MOVDIR64B instruction Fenghua Yu
2018-10-25 5:46 ` tip-bot for Fenghua Yu [this message]
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