From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753130AbbIVOKd (ORCPT ); Tue, 22 Sep 2015 10:10:33 -0400 Received: from terminus.zytor.com ([198.137.202.10]:49937 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751112AbbIVOKc (ORCPT ); Tue, 22 Sep 2015 10:10:32 -0400 Date: Tue, 22 Sep 2015 07:09:50 -0700 From: tip-bot for Ludovic Desroches Message-ID: Cc: jason@lakedaemon.net, ludovic.desroches@atmel.com, hpa@zytor.com, linux-arm-kernel@lists.infradead.org, mingo@kernel.org, marc.zyngier@arm.com, nicolas.ferre@atmel.com, tglx@linutronix.de, alexandre.belloni@free-electrons.com, Wenyou.Yang@atmel.com, boris.brezillon@free-electrons.com, sasha.levin@oracle.com, linux-kernel@vger.kernel.org Reply-To: tglx@linutronix.de, nicolas.ferre@atmel.com, linux-kernel@vger.kernel.org, alexandre.belloni@free-electrons.com, Wenyou.Yang@atmel.com, boris.brezillon@free-electrons.com, sasha.levin@oracle.com, ludovic.desroches@atmel.com, jason@lakedaemon.net, mingo@kernel.org, marc.zyngier@arm.com, hpa@zytor.com, linux-arm-kernel@lists.infradead.org In-Reply-To: <1442843173-2390-3-git-send-email-ludovic.desroches@atmel.com> References: <1442843173-2390-3-git-send-email-ludovic.desroches@atmel.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:irq/core] irqchip/atmel-aic5: Simplify base chip selection Git-Commit-ID: b55a3bb8650ddb096624175c55176d7fdbcad4ae X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: b55a3bb8650ddb096624175c55176d7fdbcad4ae Gitweb: http://git.kernel.org/tip/b55a3bb8650ddb096624175c55176d7fdbcad4ae Author: Ludovic Desroches AuthorDate: Mon, 21 Sep 2015 15:46:06 +0200 Committer: Thomas Gleixner CommitDate: Tue, 22 Sep 2015 16:04:43 +0200 irqchip/atmel-aic5: Simplify base chip selection Use irq_get_domain_generic_chip() to select the base chip. Signed-off-by: Ludovic Desroches Acked-by: Nicholas Ferre Acked-by: Boris Brezillon Cc: Cc: Cc: Cc: Cc: Cc: Link: http://lkml.kernel.org/r/1442843173-2390-3-git-send-email-ludovic.desroches@atmel.com Signed-off-by: Thomas Gleixner --- drivers/irqchip/irq-atmel-aic5.c | 28 ++++++++++------------------ 1 file changed, 10 insertions(+), 18 deletions(-) diff --git a/drivers/irqchip/irq-atmel-aic5.c b/drivers/irqchip/irq-atmel-aic5.c index ae2fcf9..62bb840 100644 --- a/drivers/irqchip/irq-atmel-aic5.c +++ b/drivers/irqchip/irq-atmel-aic5.c @@ -70,8 +70,7 @@ static struct irq_domain *aic5_domain; static asmlinkage void __exception_irq_entry aic5_handle(struct pt_regs *regs) { - struct irq_domain_chip_generic *dgc = aic5_domain->gc; - struct irq_chip_generic *bgc = dgc->gc[0]; + struct irq_chip_generic *bgc = irq_get_domain_generic_chip(aic5_domain, 0); u32 irqnr; u32 irqstat; @@ -87,8 +86,7 @@ aic5_handle(struct pt_regs *regs) static void aic5_mask(struct irq_data *d) { struct irq_domain *domain = d->domain; - struct irq_domain_chip_generic *dgc = domain->gc; - struct irq_chip_generic *bgc = dgc->gc[0]; + struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0); struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); /* @@ -105,8 +103,7 @@ static void aic5_mask(struct irq_data *d) static void aic5_unmask(struct irq_data *d) { struct irq_domain *domain = d->domain; - struct irq_domain_chip_generic *dgc = domain->gc; - struct irq_chip_generic *bgc = dgc->gc[0]; + struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0); struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); /* @@ -123,8 +120,7 @@ static void aic5_unmask(struct irq_data *d) static int aic5_retrigger(struct irq_data *d) { struct irq_domain *domain = d->domain; - struct irq_domain_chip_generic *dgc = domain->gc; - struct irq_chip_generic *bgc = dgc->gc[0]; + struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0); /* Enable interrupt on AIC5 */ irq_gc_lock(bgc); @@ -138,8 +134,7 @@ static int aic5_retrigger(struct irq_data *d) static int aic5_set_type(struct irq_data *d, unsigned type) { struct irq_domain *domain = d->domain; - struct irq_domain_chip_generic *dgc = domain->gc; - struct irq_chip_generic *bgc = dgc->gc[0]; + struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0); unsigned int smr; int ret; @@ -159,7 +154,7 @@ static void aic5_suspend(struct irq_data *d) { struct irq_domain *domain = d->domain; struct irq_domain_chip_generic *dgc = domain->gc; - struct irq_chip_generic *bgc = dgc->gc[0]; + struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0); struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); int i; u32 mask; @@ -183,7 +178,7 @@ static void aic5_resume(struct irq_data *d) { struct irq_domain *domain = d->domain; struct irq_domain_chip_generic *dgc = domain->gc; - struct irq_chip_generic *bgc = dgc->gc[0]; + struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0); struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); int i; u32 mask; @@ -207,7 +202,7 @@ static void aic5_pm_shutdown(struct irq_data *d) { struct irq_domain *domain = d->domain; struct irq_domain_chip_generic *dgc = domain->gc; - struct irq_chip_generic *bgc = dgc->gc[0]; + struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0); struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); int i; @@ -262,12 +257,11 @@ static int aic5_irq_domain_xlate(struct irq_domain *d, irq_hw_number_t *out_hwirq, unsigned int *out_type) { - struct irq_domain_chip_generic *dgc = d->gc; - struct irq_chip_generic *bgc; + struct irq_chip_generic *bgc = irq_get_domain_generic_chip(d, 0); unsigned smr; int ret; - if (!dgc) + if (!bgc) return -EINVAL; ret = aic_common_irq_domain_xlate(d, ctrlr, intspec, intsize, @@ -275,8 +269,6 @@ static int aic5_irq_domain_xlate(struct irq_domain *d, if (ret) return ret; - bgc = dgc->gc[0]; - irq_gc_lock(bgc); irq_reg_writel(bgc, *out_hwirq, AT91_AIC5_SSR); smr = irq_reg_readl(bgc, AT91_AIC5_SMR);