From: tip-bot for Marc Zyngier <tipbot@zytor.com>
To: linux-tip-commits@vger.kernel.org
Cc: tnhuynh@apm.com, mingo@kernel.org, yvo@apm.com, toanle@apm.com,
bjorn@kryo.se, sboyd@codeaurora.org, adharmap@codeaurora.org,
linus.walleij@linaro.org, arnd@arndb.de, jason@lakedaemon.net,
linux-kernel@vger.kernel.org, pvo@apm.com, hpa@zytor.com,
marc.zyngier@arm.com, tglx@linutronix.de
Subject: [tip:irq/core] irqchip: GICv3: Add support for irq_[get, set] _irqchip_state()
Date: Wed, 8 Apr 2015 14:31:31 -0700 [thread overview]
Message-ID: <tip-b594c6e20c7ff65e0f0775cb1866e97501c96846@git.kernel.org> (raw)
In-Reply-To: <1426676484-21812-4-git-send-email-marc.zyngier@arm.com>
Commit-ID: b594c6e20c7ff65e0f0775cb1866e97501c96846
Gitweb: http://git.kernel.org/tip/b594c6e20c7ff65e0f0775cb1866e97501c96846
Author: Marc Zyngier <marc.zyngier@arm.com>
AuthorDate: Wed, 18 Mar 2015 11:01:24 +0000
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitDate: Wed, 8 Apr 2015 23:28:28 +0200
irqchip: GICv3: Add support for irq_[get, set]_irqchip_state()
Add the required hooks for the internal state of an interrupt
to be exposed to other subsystems.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Phong Vo <pvo@apm.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Tin Huynh <tnhuynh@apm.com>
Cc: Y Vo <yvo@apm.com>
Cc: Toan Le <toanle@apm.com>
Cc: Bjorn Andersson <bjorn@kryo.se>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Arnd Bergmann <arnd@arndb.de>
Link: http://lkml.kernel.org/r/1426676484-21812-4-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
drivers/irqchip/irq-gic-v3.c | 83 +++++++++++++++++++++++++++++++++++++-------
1 file changed, 70 insertions(+), 13 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index fd8850d..4f2fb62 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -195,6 +195,19 @@ static void gic_enable_redist(bool enable)
/*
* Routines to disable, enable, EOI and route interrupts
*/
+static int gic_peek_irq(struct irq_data *d, u32 offset)
+{
+ u32 mask = 1 << (gic_irq(d) % 32);
+ void __iomem *base;
+
+ if (gic_irq_in_rdist(d))
+ base = gic_data_rdist_sgi_base();
+ else
+ base = gic_data.dist_base;
+
+ return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask);
+}
+
static void gic_poke_irq(struct irq_data *d, u32 offset)
{
u32 mask = 1 << (gic_irq(d) % 32);
@@ -223,6 +236,61 @@ static void gic_unmask_irq(struct irq_data *d)
gic_poke_irq(d, GICD_ISENABLER);
}
+static int gic_irq_set_irqchip_state(struct irq_data *d,
+ enum irqchip_irq_state which, bool val)
+{
+ u32 reg;
+
+ if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */
+ return -EINVAL;
+
+ switch (which) {
+ case IRQCHIP_STATE_PENDING:
+ reg = val ? GICD_ISPENDR : GICD_ICPENDR;
+ break;
+
+ case IRQCHIP_STATE_ACTIVE:
+ reg = val ? GICD_ISACTIVER : GICD_ICACTIVER;
+ break;
+
+ case IRQCHIP_STATE_MASKED:
+ reg = val ? GICD_ICENABLER : GICD_ISENABLER;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ gic_poke_irq(d, reg);
+ return 0;
+}
+
+static int gic_irq_get_irqchip_state(struct irq_data *d,
+ enum irqchip_irq_state which, bool *val)
+{
+ if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */
+ return -EINVAL;
+
+ switch (which) {
+ case IRQCHIP_STATE_PENDING:
+ *val = gic_peek_irq(d, GICD_ISPENDR);
+ break;
+
+ case IRQCHIP_STATE_ACTIVE:
+ *val = gic_peek_irq(d, GICD_ISACTIVER);
+ break;
+
+ case IRQCHIP_STATE_MASKED:
+ *val = !gic_peek_irq(d, GICD_ISENABLER);
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static void gic_eoi_irq(struct irq_data *d)
{
gic_write_eoir(gic_irq(d));
@@ -418,19 +486,6 @@ static void gic_cpu_init(void)
}
#ifdef CONFIG_SMP
-static int gic_peek_irq(struct irq_data *d, u32 offset)
-{
- u32 mask = 1 << (gic_irq(d) % 32);
- void __iomem *base;
-
- if (gic_irq_in_rdist(d))
- base = gic_data_rdist_sgi_base();
- else
- base = gic_data.dist_base;
-
- return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask);
-}
-
static int gic_secondary_init(struct notifier_block *nfb,
unsigned long action, void *hcpu)
{
@@ -601,6 +656,8 @@ static struct irq_chip gic_chip = {
.irq_eoi = gic_eoi_irq,
.irq_set_type = gic_set_type,
.irq_set_affinity = gic_set_affinity,
+ .irq_get_irqchip_state = gic_irq_get_irqchip_state,
+ .irq_set_irqchip_state = gic_irq_set_irqchip_state,
};
#define GIC_ID_NR (1U << gic_data.rdists.id_bits)
next prev parent reply other threads:[~2015-04-08 21:32 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-18 11:01 [PATCH v4 0/3] genirq: Saving/restoring the irqchip state of an irq line Marc Zyngier
2015-03-18 11:01 ` [PATCH v4 1/3] genirq: Allow the irqchip state of an IRQ to be save/restored Marc Zyngier
2015-04-08 17:48 ` Bjorn Andersson
2015-04-13 16:18 ` Srinivas Kandagatla
2015-04-13 16:21 ` Marc Zyngier
2015-04-08 21:30 ` [tip:irq/core] " tip-bot for Marc Zyngier
2015-03-18 11:01 ` [PATCH v4 2/3] irqchip: GIC: Add support for irq_{get,set}_irqchip_state Marc Zyngier
2015-04-08 21:31 ` [tip:irq/core] irqchip: GIC: Add support for irq_[get, set] _irqchip_state() tip-bot for Marc Zyngier
2015-05-13 2:25 ` [PATCH v4 2/3] irqchip: GIC: Add support for irq_{get,set}_irqchip_state Feng Kan
2015-05-13 11:58 ` Linus Walleij
2015-05-13 15:44 ` Feng Kan
2015-05-14 10:32 ` Linus Walleij
2015-05-14 20:14 ` Feng Kan
2015-05-19 8:40 ` Linus Walleij
2015-05-19 10:01 ` Marc Zyngier
2015-05-19 15:01 ` Linus Walleij
2015-05-19 21:45 ` Feng Kan
2015-05-20 7:58 ` Marc Zyngier
2015-03-18 11:01 ` [PATCH v4 3/3] irqchip: GICv3: " Marc Zyngier
2015-04-08 21:31 ` tip-bot for Marc Zyngier [this message]
2015-04-13 14:12 ` [PATCH v4 0/3] genirq: Saving/restoring the irqchip state of an irq line Eric Auger
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