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From: tip-bot for Vince Weaver <tipbot@zytor.com>
To: linux-tip-commits@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, hpa@zytor.com, mingo@kernel.org,
	torvalds@linux-foundation.org, peterz@infradead.org,
	acme@kernel.org, vincent.weaver@maine.edu, tglx@linutronix.de
Subject: [tip:perf/core] perf/x86: Use common PMU interrupt disabled code
Date: Thu, 5 Jun 2014 07:38:44 -0700	[thread overview]
Message-ID: <tip-c184c980de30dc5f6fec4b281928aa6743708da9@git.kernel.org> (raw)
In-Reply-To: <alpine.DEB.2.10.1405161715560.11099@vincent-weaver-1.umelst.maine.edu>

Commit-ID:  c184c980de30dc5f6fec4b281928aa6743708da9
Gitweb:     http://git.kernel.org/tip/c184c980de30dc5f6fec4b281928aa6743708da9
Author:     Vince Weaver <vincent.weaver@maine.edu>
AuthorDate: Fri, 16 May 2014 17:18:07 -0400
Committer:  Ingo Molnar <mingo@kernel.org>
CommitDate: Thu, 5 Jun 2014 12:30:03 +0200

perf/x86: Use common PMU interrupt disabled code

Make the x86 perf code use the new common PMU interrupt disabled code.

Typically most x86 machines have working PMU interrupts, although
some older p6-class machines had this problem.

Signed-off-by: Vince Weaver <vincent.weaver@maine.edu>
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Link: http://lkml.kernel.org/r/alpine.DEB.2.10.1405161715560.11099@vincent-weaver-1.umelst.maine.edu
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
 arch/x86/kernel/cpu/perf_event.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index 32029e3..2bdfbff 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -303,15 +303,6 @@ int x86_setup_perfctr(struct perf_event *event)
 		hwc->sample_period = x86_pmu.max_period;
 		hwc->last_period = hwc->sample_period;
 		local64_set(&hwc->period_left, hwc->sample_period);
-	} else {
-		/*
-		 * If we have a PMU initialized but no APIC
-		 * interrupts, we cannot sample hardware
-		 * events (user-space has to fall back and
-		 * sample via a hrtimer based software event):
-		 */
-		if (!x86_pmu.apic)
-			return -EOPNOTSUPP;
 	}
 
 	if (attr->type == PERF_TYPE_RAW)
@@ -1367,6 +1358,15 @@ static void __init pmu_check_apic(void)
 	x86_pmu.apic = 0;
 	pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
 	pr_info("no hardware sampling interrupt available.\n");
+
+	/*
+	 * If we have a PMU initialized but no APIC
+	 * interrupts, we cannot sample hardware
+	 * events (user-space has to fall back and
+	 * sample via a hrtimer based software event):
+	 */
+	pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
+
 }
 
 static struct attribute_group x86_pmu_format_group = {

      reply	other threads:[~2014-06-05 14:39 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-05-16 21:07 [PATCH 0/3] perf: disable sampled events if no PMU interrupt Vince Weaver
2014-05-16 21:12 ` [PATCH 1/3] " Vince Weaver
2014-05-19 16:01   ` Will Deacon
2014-05-20  9:12   ` Peter Zijlstra
2014-05-20 13:19     ` Vince Weaver
2014-05-20 13:27       ` Peter Zijlstra
2014-06-05 14:38   ` [tip:perf/core] perf: Disable " tip-bot for Vince Weaver
2014-05-16 21:15 ` [PATCH 2/3] perf, ARM: use common PMU interrupt disabled code Vince Weaver
2014-05-19 15:57   ` Will Deacon
2014-05-20  9:12     ` Peter Zijlstra
2014-06-05 14:38   ` [tip:perf/core] perf/ARM: Use " tip-bot for Vince Weaver
2014-05-16 21:18 ` [PATCH 3/3] perf,x86: use " Vince Weaver
2014-06-05 14:38   ` tip-bot for Vince Weaver [this message]

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