From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756754AbbIVOBc (ORCPT ); Tue, 22 Sep 2015 10:01:32 -0400 Received: from terminus.zytor.com ([198.137.202.10]:49817 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752596AbbIVOBb (ORCPT ); Tue, 22 Sep 2015 10:01:31 -0400 Date: Tue, 22 Sep 2015 07:00:32 -0700 From: tip-bot for Ludovic Desroches Message-ID: Cc: ludovic.desroches@atmel.com, alexandre.belloni@free-electrons.com, Wenyou.Yang@atmel.com, nicolas.ferre@atmel.com, hpa@zytor.com, jason@lakedaemon.net, tglx@linutronix.de, linux-arm-kernel@lists.infradead.org, boris.brezillon@free-electrons.com, linux-kernel@vger.kernel.org, mingo@kernel.org, marc.zyngier@arm.com, sasha.levin@oracle.com Reply-To: ludovic.desroches@atmel.com, nicolas.ferre@atmel.com, Wenyou.Yang@atmel.com, alexandre.belloni@free-electrons.com, jason@lakedaemon.net, hpa@zytor.com, linux-arm-kernel@lists.infradead.org, tglx@linutronix.de, boris.brezillon@free-electrons.com, mingo@kernel.org, linux-kernel@vger.kernel.org, sasha.levin@oracle.com, marc.zyngier@arm.com In-Reply-To: <1442843173-2390-1-git-send-email-ludovic.desroches@atmel.com> References: <1442843173-2390-1-git-send-email-ludovic.desroches@atmel.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:irq/urgent] irqchip/atmel-aic5: Use per chip mask caches in mask/unmask() Git-Commit-ID: d32dc9aa10c739363c775baf4499416b2e0dc11f X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: d32dc9aa10c739363c775baf4499416b2e0dc11f Gitweb: http://git.kernel.org/tip/d32dc9aa10c739363c775baf4499416b2e0dc11f Author: Ludovic Desroches AuthorDate: Mon, 21 Sep 2015 15:46:04 +0200 Committer: Thomas Gleixner CommitDate: Tue, 22 Sep 2015 15:55:51 +0200 irqchip/atmel-aic5: Use per chip mask caches in mask/unmask() When masking/unmasking interrupts, mask_cache is updated and used later for suspend/resume. Unfortunately, it always was the mask_cache associated with the first irq chip which was updated. So when performing resume, only irqs 0-31 could be enabled. Fixes: b1479ebb7720 ("irqchip: atmel-aic: Add atmel AIC/AIC5 drivers") Signed-off-by: Ludovic Desroches Cc: Cc: Cc: Cc: Cc: Cc: Cc: Cc: Cc: stable@vger.kernel.org #3.18 Link: http://lkml.kernel.org/r/1442843173-2390-1-git-send-email-ludovic.desroches@atmel.com Signed-off-by: Thomas Gleixner --- drivers/irqchip/irq-atmel-aic5.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/drivers/irqchip/irq-atmel-aic5.c b/drivers/irqchip/irq-atmel-aic5.c index 9da9942..f6d6804 100644 --- a/drivers/irqchip/irq-atmel-aic5.c +++ b/drivers/irqchip/irq-atmel-aic5.c @@ -88,28 +88,36 @@ static void aic5_mask(struct irq_data *d) { struct irq_domain *domain = d->domain; struct irq_domain_chip_generic *dgc = domain->gc; - struct irq_chip_generic *gc = dgc->gc[0]; + struct irq_chip_generic *bgc = dgc->gc[0]; + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); - /* Disable interrupt on AIC5 */ - irq_gc_lock(gc); + /* + * Disable interrupt on AIC5. We always take the lock of the + * first irq chip as all chips share the same registers. + */ + irq_gc_lock(bgc); irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR); irq_reg_writel(gc, 1, AT91_AIC5_IDCR); gc->mask_cache &= ~d->mask; - irq_gc_unlock(gc); + irq_gc_unlock(bgc); } static void aic5_unmask(struct irq_data *d) { struct irq_domain *domain = d->domain; struct irq_domain_chip_generic *dgc = domain->gc; - struct irq_chip_generic *gc = dgc->gc[0]; + struct irq_chip_generic *bgc = dgc->gc[0]; + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); - /* Enable interrupt on AIC5 */ - irq_gc_lock(gc); + /* + * Enable interrupt on AIC5. We always take the lock of the + * first irq chip as all chips share the same registers. + */ + irq_gc_lock(bgc); irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR); irq_reg_writel(gc, 1, AT91_AIC5_IECR); gc->mask_cache |= d->mask; - irq_gc_unlock(gc); + irq_gc_unlock(bgc); } static int aic5_retrigger(struct irq_data *d)