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* [PATCH v2 0/2] x86/cpu/AMD: Make LFENCE a serializing instruction on AMD
@ 2018-01-08 22:09 Tom Lendacky
  2018-01-08 22:09 ` [PATCH v2 1/2] x86/cpu/AMD: Make LFENCE a serializing instruction Tom Lendacky
                   ` (3 more replies)
  0 siblings, 4 replies; 8+ messages in thread
From: Tom Lendacky @ 2018-01-08 22:09 UTC (permalink / raw)
  To: x86, linux-kernel
  Cc: Peter Zijlstra, Linus Torvalds, Dan Williams, Dave Hansen,
	Borislav Petkov, Thomas Gleixner, Tim Chen, Greg Kroah-Hartman,
	David Woodhouse, Paul Turner

To aid in speculation control, the LFENCE instruction will be turned into
a serializing instruction. There is less performance impact using LFENCE
in this way compared to MFENCE.

With LFENCE now being a serializing instruction, it can be also used in
rdtsc_ordered() in preference to MFENCE_RDTSC.  Since the kernel could
be running under a hypervisor that does not allow writing to that MSR,
it must be first verified that the write was successful before setting
the LFENCE_RDTSC feature.

The following patches are included in this series:
- Make LFENCE a serializing instruction on AMD
- Use LFENCE_RDTSC in preference to MFENCE_RDTSC on AMD

This patch series is based on tip:x86/pti.

---

Changes from v1:
- Add a check verifying the MSR was actually updated
- Remove the third patch that eliminates the MFENCE_RDTSC feature
  (since the feature is still needed)
- Adding Dan Williams to the cc since this will impact nospec_barrier(),
  which will require an alternative_2 to add an MFENCE instruction with
  an MFENCE_RDTSC check

Tom Lendacky (2):
      x86/cpu/AMD: Make LFENCE a serializing instruction
      x86/cpu/AMD: Use LFENCE_RDTSC in preference to MFENCE_RDTSC


 arch/x86/include/asm/msr-index.h |    3 +++
 arch/x86/kernel/cpu/amd.c        |   27 +++++++++++++++++++++++++--
 2 files changed, 28 insertions(+), 2 deletions(-)

-- 
Tom Lendacky

^ permalink raw reply	[flat|nested] 8+ messages in thread
* [PATCH v1 1/3] x86/cpu/AMD: Make LFENCE a serializing instruction
@ 2018-01-05 16:07 Tom Lendacky
  2018-01-06 21:05 ` [tip:x86/pti] " tip-bot for Tom Lendacky
  0 siblings, 1 reply; 8+ messages in thread
From: Tom Lendacky @ 2018-01-05 16:07 UTC (permalink / raw)
  To: x86, linux-kernel
  Cc: Peter Zijlstra, Linus Torvalds, Dave Hansen, Borislav Petkov,
	Thomas Gleixner, Tim Chen, Greg Kroah-Hartman, David Woodhouse,
	Paul Turner

To aid in speculation control, make LFENCE a serializing instruction.
This is done by setting bit 1 of MSR 0xc0011029 (DE_CFG).  Some families
that support LFENCE do not have this MSR.  For these families, the LFENCE
instruction is already serializing.

Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
---
 arch/x86/include/asm/msr-index.h |    2 ++
 arch/x86/kernel/cpu/amd.c        |    9 +++++++++
 2 files changed, 11 insertions(+)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index ab02261..1e7d710 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -352,6 +352,8 @@
 #define FAM10H_MMIO_CONF_BASE_MASK	0xfffffffULL
 #define FAM10H_MMIO_CONF_BASE_SHIFT	20
 #define MSR_FAM10H_NODE_ID		0xc001100c
+#define MSR_F10H_DECFG			0xc0011029
+#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT	1
 
 /* K8 MSRs */
 #define MSR_K8_TOP_MEM1			0xc001001a
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index bcb75dc..fbd439e 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -829,6 +829,15 @@ static void init_amd(struct cpuinfo_x86 *c)
 		set_cpu_cap(c, X86_FEATURE_K8);
 
 	if (cpu_has(c, X86_FEATURE_XMM2)) {
+		/*
+		 * Use LFENCE for execution serialization. On families which
+		 * don't have that MSR, LFENCE is already serializing.
+		 * msr_set_bit() uses the safe accessors, too, even if the MSR
+		 * is not present.
+		 */
+		msr_set_bit(MSR_F10H_DECFG,
+			    MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);
+
 		/* MFENCE stops RDTSC speculation */
 		set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
 	}

^ permalink raw reply related	[flat|nested] 8+ messages in thread

end of thread, other threads:[~2018-01-09  0:54 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-01-08 22:09 [PATCH v2 0/2] x86/cpu/AMD: Make LFENCE a serializing instruction on AMD Tom Lendacky
2018-01-08 22:09 ` [PATCH v2 1/2] x86/cpu/AMD: Make LFENCE a serializing instruction Tom Lendacky
2018-01-09  0:48   ` [tip:x86/pti] " tip-bot for Tom Lendacky
2018-01-08 22:09 ` [PATCH v2 2/2] x86/cpu/AMD: Use LFENCE_RDTSC in preference to MFENCE_RDTSC Tom Lendacky
2018-01-09  0:49   ` [tip:x86/pti] " tip-bot for Tom Lendacky
2018-01-08 22:34 ` [PATCH v2 0/2] x86/cpu/AMD: Make LFENCE a serializing instruction on AMD Dan Williams
2018-01-08 23:52 ` Borislav Petkov
  -- strict thread matches above, loose matches on Subject: below --
2018-01-05 16:07 [PATCH v1 1/3] x86/cpu/AMD: Make LFENCE a serializing instruction Tom Lendacky
2018-01-06 21:05 ` [tip:x86/pti] " tip-bot for Tom Lendacky

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