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From: tip-bot for Andi Kleen <tipbot@zytor.com>
To: linux-tip-commits@vger.kernel.org
Cc: vincent.weaver@maine.edu, mingo@kernel.org,
	linux-kernel@vger.kernel.org, eranian@google.com,
	jolsa@redhat.com, peterz@infradead.org, acme@redhat.com,
	torvalds@linux-foundation.org,
	alexander.shishkin@linux.intel.com, ak@linux.intel.com,
	tglx@linutronix.de, hpa@zytor.com
Subject: [tip:perf/core] perf/x86/intel: Add topdown events to Intel Atom
Date: Fri, 3 Jun 2016 03:53:58 -0700
Message-ID: <tip-eb12b8ece71cfd4c96df37198b9903fc639768d8@git.kernel.org> (raw)
In-Reply-To: <1463703002-19686-5-git-send-email-andi@firstfloor.org>

Commit-ID:  eb12b8ece71cfd4c96df37198b9903fc639768d8
Gitweb:     http://git.kernel.org/tip/eb12b8ece71cfd4c96df37198b9903fc639768d8
Author:     Andi Kleen <ak@linux.intel.com>
AuthorDate: Thu, 19 May 2016 17:09:58 -0700
Committer:  Ingo Molnar <mingo@kernel.org>
CommitDate: Fri, 3 Jun 2016 09:41:24 +0200

perf/x86/intel: Add topdown events to Intel Atom

Add topdown event declarations to Silvermont / Airmont.
These cores do not support the full Top Down metrics, but an useful
subset (FrontendBound, Retiring, Backend Bound/Bad Speculation).

The perf stat tool automatically handles the missing events
and combines the available metrics.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Cc: acme@kernel.org
Cc: jolsa@kernel.org
Link: http://lkml.kernel.org/r/1463703002-19686-5-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
 arch/x86/events/intel/core.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 4f51bc4..593b167 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -1367,6 +1367,29 @@ static __initconst const u64 atom_hw_cache_event_ids
  },
 };
 
+EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c");
+EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2");
+/* no_alloc_cycles.not_delivered */
+EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm,
+	       "event=0xca,umask=0x50");
+EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2");
+/* uops_retired.all */
+EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm,
+	       "event=0xc2,umask=0x10");
+/* uops_retired.all */
+EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm,
+	       "event=0xc2,umask=0x10");
+
+static struct attribute *slm_events_attrs[] = {
+	EVENT_PTR(td_total_slots_slm),
+	EVENT_PTR(td_total_slots_scale_slm),
+	EVENT_PTR(td_fetch_bubbles_slm),
+	EVENT_PTR(td_fetch_bubbles_scale_slm),
+	EVENT_PTR(td_slots_issued_slm),
+	EVENT_PTR(td_slots_retired_slm),
+	NULL
+};
+
 static struct extra_reg intel_slm_extra_regs[] __read_mostly =
 {
 	/* must define OFFCORE_RSP_X first, see intel_fixup_er() */
@@ -3629,6 +3652,7 @@ __init int intel_pmu_init(void)
 		x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
 		x86_pmu.extra_regs = intel_slm_extra_regs;
 		x86_pmu.flags |= PMU_FL_HAS_RSP_1;
+		x86_pmu.cpu_events = slm_events_attrs;
 		pr_cont("Silvermont events, ");
 		break;
 

  reply index

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-05-20  0:09 Add top down metrics to perf stat Andi Kleen
2016-05-20  0:09 ` [PATCH 1/8] x86/topology: Add topology_max_smt_threads() Andi Kleen
2016-06-03 10:52   ` [tip:perf/core] " tip-bot for Andi Kleen
2016-05-20  0:09 ` [PATCH 2/8] perf/x86: Support sysfs files depending on SMT status Andi Kleen
2016-06-03 10:53   ` [tip:perf/core] " tip-bot for Andi Kleen
2016-05-20  0:09 ` [PATCH 3/8] perf/x86/intel: Add Top Down events to Intel Core Andi Kleen
2016-06-03 10:53   ` [tip:perf/core] perf/x86/intel: Add topdown " tip-bot for Andi Kleen
2016-05-20  0:09 ` [PATCH 4/8] perf/x86/intel: Add Top Down events to Intel Atom Andi Kleen
2016-06-03 10:53   ` tip-bot for Andi Kleen [this message]
2016-05-20  0:09 ` [PATCH 5/8] perf/x86/intel: Use new topology_max_smt_threads() in HT leak workaround Andi Kleen
2016-06-03 10:54   ` [tip:perf/core] " tip-bot for Andi Kleen
2016-05-20  0:10 ` [PATCH 6/8] perf stat: Avoid fractional digits for integer scales Andi Kleen
2016-05-23 14:36   ` Arnaldo Carvalho de Melo
2016-05-20  0:10 ` [PATCH 7/8] perf stat: Basic support for TopDown in perf stat Andi Kleen
2016-05-23 14:40   ` Arnaldo Carvalho de Melo
2016-05-20  0:10 ` [PATCH 8/8] perf stat: Add computation of TopDown formulas Andi Kleen

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