From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751863AbcF0MzH (ORCPT ); Mon, 27 Jun 2016 08:55:07 -0400 Received: from terminus.zytor.com ([198.137.202.10]:41498 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750869AbcF0MzD (ORCPT ); Mon, 27 Jun 2016 08:55:03 -0400 Date: Mon, 27 Jun 2016 05:54:18 -0700 From: tip-bot for David Carrillo-Cisneros Message-ID: Cc: hpa@zytor.com, vincent.weaver@maine.edu, linux-kernel@vger.kernel.org, kan.liang@intel.com, acme@redhat.com, eranian@google.com, ak@linux.intel.com, mingo@kernel.org, alexander.shishkin@linux.intel.com, tglx@linutronix.de, davidcc@google.com, torvalds@linux-foundation.org, jolsa@redhat.com, peterz@infradead.org Reply-To: jolsa@redhat.com, torvalds@linux-foundation.org, peterz@infradead.org, davidcc@google.com, tglx@linutronix.de, alexander.shishkin@linux.intel.com, eranian@google.com, ak@linux.intel.com, mingo@kernel.org, acme@redhat.com, linux-kernel@vger.kernel.org, kan.liang@intel.com, vincent.weaver@maine.edu, hpa@zytor.com In-Reply-To: <1466533874-52003-2-git-send-email-davidcc@google.com> References: <1466533874-52003-2-git-send-email-davidcc@google.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:perf/core] perf/x86/intel: Print LBR support statement after validation Git-Commit-ID: f09509b9398b23ca53360ca57106555698ec2e93 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: f09509b9398b23ca53360ca57106555698ec2e93 Gitweb: http://git.kernel.org/tip/f09509b9398b23ca53360ca57106555698ec2e93 Author: David Carrillo-Cisneros AuthorDate: Tue, 21 Jun 2016 11:31:10 -0700 Committer: Ingo Molnar CommitDate: Mon, 27 Jun 2016 11:34:18 +0200 perf/x86/intel: Print LBR support statement after validation The following commit: 338b522ca43c ("perf/x86/intel: Protect LBR and extra_regs against KVM lying") added an additional test to LBR support detection that is performed after printing the LBR support statement to dmesg. Move the LBR support output after the very last test, to make sure we print the true status of LBR support. Signed-off-by: David Carrillo-Cisneros Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Stephane Eranian Reviewed-by: Andi Kleen Cc: Alexander Shishkin Cc: Arnaldo Carvalho de Melo Cc: Jiri Olsa Cc: Kan Liang Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: Vince Weaver Link: http://lkml.kernel.org/r/1466533874-52003-2-git-send-email-davidcc@google.com Signed-off-by: Ingo Molnar --- arch/x86/events/intel/core.c | 2 ++ arch/x86/events/intel/lbr.c | 9 --------- 2 files changed, 2 insertions(+), 9 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 3ed528c..61a027b 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3958,6 +3958,8 @@ __init int intel_pmu_init(void) x86_pmu.lbr_nr = 0; } + if (x86_pmu.lbr_nr) + pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr); /* * Access extra MSR may cause #GP under certain circumstances. * E.g. KVM doesn't support offcore event diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c index 9e2b40c..2dca66c 100644 --- a/arch/x86/events/intel/lbr.c +++ b/arch/x86/events/intel/lbr.c @@ -956,7 +956,6 @@ void __init intel_pmu_lbr_init_core(void) * SW branch filter usage: * - compensate for lack of HW filter */ - pr_cont("4-deep LBR, "); } /* nehalem/westmere */ @@ -977,7 +976,6 @@ void __init intel_pmu_lbr_init_nhm(void) * That requires LBR_FAR but that means far * jmp need to be filtered out */ - pr_cont("16-deep LBR, "); } /* sandy bridge */ @@ -997,7 +995,6 @@ void __init intel_pmu_lbr_init_snb(void) * That requires LBR_FAR but that means far * jmp need to be filtered out */ - pr_cont("16-deep LBR, "); } /* haswell */ @@ -1010,8 +1007,6 @@ void intel_pmu_lbr_init_hsw(void) x86_pmu.lbr_sel_mask = LBR_SEL_MASK; x86_pmu.lbr_sel_map = hsw_lbr_sel_map; - - pr_cont("16-deep LBR, "); } /* skylake */ @@ -1031,7 +1026,6 @@ __init void intel_pmu_lbr_init_skl(void) * That requires LBR_FAR but that means far * jmp need to be filtered out */ - pr_cont("32-deep LBR, "); } /* atom */ @@ -1057,7 +1051,6 @@ void __init intel_pmu_lbr_init_atom(void) * SW branch filter usage: * - compensate for lack of HW filter */ - pr_cont("8-deep LBR, "); } /* slm */ @@ -1088,6 +1081,4 @@ void intel_pmu_lbr_init_knl(void) x86_pmu.lbr_sel_mask = LBR_SEL_MASK; x86_pmu.lbr_sel_map = snb_lbr_sel_map; - - pr_cont("8-deep LBR, "); }