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* [PATCH v2] soc: mmsys: mediatek: add mask to mmsys routes
@ 2021-07-29  7:05 Frank Wunderlich
  2021-08-04 15:17 ` Matthias Brugger
  0 siblings, 1 reply; 3+ messages in thread
From: Frank Wunderlich @ 2021-07-29  7:05 UTC (permalink / raw)
  To: linux-mediatek
  Cc: CK Hu, Matthias Brugger, Enric Balletbo i Serra,
	linux-arm-kernel, linux-kernel, dafna.hirschfeld,
	Frank Wunderlich, Chun-Kuang Hu, Hsin-Yi Wang

From: CK Hu <ck.hu@mediatek.com>

SOUT has many bits and need to be cleared before set new value.
Write only could do the clear, but for MOUT, it clears bits that
should not be cleared. So use a mask to reset only the needed bits.

this fixes HDMI issues on MT7623/BPI-R2 since 5.13

Fixes: 440147639ac7 ("soc: mediatek: mmsys: Use an array for setting the routing registers")
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org>
---
code is taken from here (upstreamed without mask part)
https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2345186/5
basicly CK Hu's code so i set him as author
---
v2:
- added mask to mt8183 specific table (mask=value),
  before val was used as mask and val itself not defined,
  breaking display on these devices
- as changes do not add addional code only restoring same
  behaviour for mt8183 added reviwed-by from CK Hu from v1
---
 drivers/soc/mediatek/mt8183-mmsys.h |  21 +++--
 drivers/soc/mediatek/mtk-mmsys.c    |   7 +-
 drivers/soc/mediatek/mtk-mmsys.h    | 133 +++++++++++++++++++---------
 3 files changed, 112 insertions(+), 49 deletions(-)

diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h
index 579dfc8dc8fc..9dee485807c9 100644
--- a/drivers/soc/mediatek/mt8183-mmsys.h
+++ b/drivers/soc/mediatek/mt8183-mmsys.h
@@ -28,25 +28,32 @@
 static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
 	{
 		DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
-		MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L
+		MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L,
+		MT8183_OVL0_MOUT_EN_OVL0_2L
 	}, {
 		DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
-		MT8183_DISP_OVL0_2L_MOUT_EN, MT8183_OVL0_2L_MOUT_EN_DISP_PATH0
+		MT8183_DISP_OVL0_2L_MOUT_EN, MT8183_OVL0_2L_MOUT_EN_DISP_PATH0,
+		MT8183_OVL0_2L_MOUT_EN_DISP_PATH0
 	}, {
 		DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_RDMA1,
-		MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1
+		MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1,
+		MT8183_OVL1_2L_MOUT_EN_RDMA1
 	}, {
 		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
-		MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0
+		MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0,
+		MT8183_DITHER0_MOUT_IN_DSI0
 	}, {
 		DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
-		MT8183_DISP_PATH0_SEL_IN, MT8183_DISP_PATH0_SEL_IN_OVL0_2L
+		MT8183_DISP_PATH0_SEL_IN, MT8183_DISP_PATH0_SEL_IN_OVL0_2L,
+		MT8183_DISP_PATH0_SEL_IN_OVL0_2L
 	}, {
 		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
-		MT8183_DISP_DPI0_SEL_IN, MT8183_DPI0_SEL_IN_RDMA1
+		MT8183_DISP_DPI0_SEL_IN, MT8183_DPI0_SEL_IN_RDMA1,
+		MT8183_DPI0_SEL_IN_RDMA1
 	}, {
 		DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
-		MT8183_DISP_RDMA0_SOUT_SEL_IN, MT8183_RDMA0_SOUT_COLOR0
+		MT8183_DISP_RDMA0_SOUT_SEL_IN, MT8183_RDMA0_SOUT_COLOR0,
+		MT8183_RDMA0_SOUT_COLOR0
 	}
 };
 
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 080660ef11bf..0f949896fd06 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -68,7 +68,9 @@ void mtk_mmsys_ddp_connect(struct device *dev,
 
 	for (i = 0; i < mmsys->data->num_routes; i++)
 		if (cur == routes[i].from_comp && next == routes[i].to_comp) {
-			reg = readl_relaxed(mmsys->regs + routes[i].addr) | routes[i].val;
+			reg = readl_relaxed(mmsys->regs + routes[i].addr);
+			reg &= ~routes[i].mask;
+			reg |= routes[i].val;
 			writel_relaxed(reg, mmsys->regs + routes[i].addr);
 		}
 }
@@ -85,7 +87,8 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
 
 	for (i = 0; i < mmsys->data->num_routes; i++)
 		if (cur == routes[i].from_comp && next == routes[i].to_comp) {
-			reg = readl_relaxed(mmsys->regs + routes[i].addr) & ~routes[i].val;
+			reg = readl_relaxed(mmsys->regs + routes[i].addr);
+			reg &= ~routes[i].mask;
 			writel_relaxed(reg, mmsys->regs + routes[i].addr);
 		}
 }
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index a760a34e6eca..5f3e2bf0c40b 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -35,41 +35,54 @@
 #define RDMA0_SOUT_DSI1				0x1
 #define RDMA0_SOUT_DSI2				0x4
 #define RDMA0_SOUT_DSI3				0x5
+#define RDMA0_SOUT_MASK				0x7
 #define RDMA1_SOUT_DPI0				0x2
 #define RDMA1_SOUT_DPI1				0x3
 #define RDMA1_SOUT_DSI1				0x1
 #define RDMA1_SOUT_DSI2				0x4
 #define RDMA1_SOUT_DSI3				0x5
+#define RDMA1_SOUT_MASK				0x7
 #define RDMA2_SOUT_DPI0				0x2
 #define RDMA2_SOUT_DPI1				0x3
 #define RDMA2_SOUT_DSI1				0x1
 #define RDMA2_SOUT_DSI2				0x4
 #define RDMA2_SOUT_DSI3				0x5
+#define RDMA2_SOUT_MASK				0x7
 #define DPI0_SEL_IN_RDMA1			0x1
 #define DPI0_SEL_IN_RDMA2			0x3
+#define DPI0_SEL_IN_MASK			0x3
 #define DPI1_SEL_IN_RDMA1			(0x1 << 8)
 #define DPI1_SEL_IN_RDMA2			(0x3 << 8)
+#define DPI1_SEL_IN_MASK			(0x3 << 8)
 #define DSI0_SEL_IN_RDMA1			0x1
 #define DSI0_SEL_IN_RDMA2			0x4
+#define DSI0_SEL_IN_MASK			0x7
 #define DSI1_SEL_IN_RDMA1			0x1
 #define DSI1_SEL_IN_RDMA2			0x4
+#define DSI1_SEL_IN_MASK			0x7
 #define DSI2_SEL_IN_RDMA1			(0x1 << 16)
 #define DSI2_SEL_IN_RDMA2			(0x4 << 16)
+#define DSI2_SEL_IN_MASK			(0x7 << 16)
 #define DSI3_SEL_IN_RDMA1			(0x1 << 16)
 #define DSI3_SEL_IN_RDMA2			(0x4 << 16)
+#define DSI3_SEL_IN_MASK			(0x7 << 16)
 #define COLOR1_SEL_IN_OVL1			0x1
 
 #define OVL_MOUT_EN_RDMA			0x1
 #define BLS_TO_DSI_RDMA1_TO_DPI1		0x8
 #define BLS_TO_DPI_RDMA1_TO_DSI			0x2
+#define BLS_RDMA1_DSI_DPI_MASK			0xf
 #define DSI_SEL_IN_BLS				0x0
 #define DPI_SEL_IN_BLS				0x0
+#define DPI_SEL_IN_MASK				0x1
 #define DSI_SEL_IN_RDMA				0x1
+#define DSI_SEL_IN_MASK				0x1
 
 struct mtk_mmsys_routes {
 	u32 from_comp;
 	u32 to_comp;
 	u32 addr;
+	u32 mask;
 	u32 val;
 };
 
@@ -91,124 +104,164 @@ struct mtk_mmsys_driver_data {
 static const struct mtk_mmsys_routes mmsys_default_routing_table[] = {
 	{
 		DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0,
-		DISP_REG_CONFIG_OUT_SEL, BLS_TO_DSI_RDMA1_TO_DPI1
+		DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK,
+		BLS_TO_DSI_RDMA1_TO_DPI1
 	}, {
 		DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0,
-		DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_BLS
+		DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK,
+		DSI_SEL_IN_BLS
 	}, {
 		DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
-		DISP_REG_CONFIG_OUT_SEL, BLS_TO_DPI_RDMA1_TO_DSI
+		DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK,
+		BLS_TO_DPI_RDMA1_TO_DSI
 	}, {
 		DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
-		DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_RDMA
+		DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK,
+		DSI_SEL_IN_RDMA
 	}, {
 		DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
-		DISP_REG_CONFIG_DPI_SEL, DPI_SEL_IN_BLS
+		DISP_REG_CONFIG_DPI_SEL, DPI_SEL_IN_MASK,
+		DPI_SEL_IN_BLS
 	}, {
 		DDP_COMPONENT_GAMMA, DDP_COMPONENT_RDMA1,
-		DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, GAMMA_MOUT_EN_RDMA1
+		DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, GAMMA_MOUT_EN_RDMA1,
+		GAMMA_MOUT_EN_RDMA1
 	}, {
 		DDP_COMPONENT_OD0, DDP_COMPONENT_RDMA0,
-		DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD_MOUT_EN_RDMA0
+		DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD_MOUT_EN_RDMA0,
+		OD_MOUT_EN_RDMA0
 	}, {
 		DDP_COMPONENT_OD1, DDP_COMPONENT_RDMA1,
-		DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD1_MOUT_EN_RDMA1
+		DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD1_MOUT_EN_RDMA1,
+		OD1_MOUT_EN_RDMA1
 	}, {
 		DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
-		DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0
+		DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
+		OVL0_MOUT_EN_COLOR0
 	}, {
 		DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
-		DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0
+		DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0,
+		COLOR0_SEL_IN_OVL0
 	}, {
 		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
-		DISP_REG_CONFIG_DISP_OVL_MOUT_EN, OVL_MOUT_EN_RDMA
+		DISP_REG_CONFIG_DISP_OVL_MOUT_EN, OVL_MOUT_EN_RDMA,
+		OVL_MOUT_EN_RDMA
 	}, {
 		DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
-		DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, OVL1_MOUT_EN_COLOR1
+		DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, OVL1_MOUT_EN_COLOR1,
+		OVL1_MOUT_EN_COLOR1
 	}, {
 		DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
-		DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1
+		DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1,
+		COLOR1_SEL_IN_OVL1
 	}, {
 		DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI0,
-		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_DPI0
+		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
+		RDMA0_SOUT_DPI0
 	}, {
 		DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI1,
-		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_DPI1
+		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
+		RDMA0_SOUT_DPI1
 	}, {
 		DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI1,
-		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_DSI1
+		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
+		RDMA0_SOUT_DSI1
 	}, {
 		DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI2,
-		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_DSI2
+		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
+		RDMA0_SOUT_DSI2
 	}, {
 		DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI3,
-		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_DSI3
+		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
+		RDMA0_SOUT_DSI3
 	}, {
 		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
-		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_DPI0
+		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
+		RDMA1_SOUT_DPI0
 	}, {
 		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
-		DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_RDMA1
+		DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK,
+		DPI0_SEL_IN_RDMA1
 	}, {
 		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1,
-		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_DPI1
+		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
+		RDMA1_SOUT_DPI1
 	}, {
 		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1,
-		DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_RDMA1
+		DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK,
+		DPI1_SEL_IN_RDMA1
 	}, {
 		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI0,
-		DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_RDMA1
+		DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK,
+		DSI0_SEL_IN_RDMA1
 	}, {
 		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1,
-		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_DSI1
+		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
+		RDMA1_SOUT_DSI1
 	}, {
 		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1,
-		DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_RDMA1
+		DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK,
+		DSI1_SEL_IN_RDMA1
 	}, {
 		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2,
-		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_DSI2
+		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
+		RDMA1_SOUT_DSI2
 	}, {
 		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2,
-		DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_RDMA1
+		DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK,
+		DSI2_SEL_IN_RDMA1
 	}, {
 		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3,
-		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_DSI3
+		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
+		RDMA1_SOUT_DSI3
 	}, {
 		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3,
-		DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_RDMA1
+		DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK,
+		DSI3_SEL_IN_RDMA1
 	}, {
 		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0,
-		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_DPI0
+		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
+		RDMA2_SOUT_DPI0
 	}, {
 		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0,
-		DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_RDMA2
+		DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK,
+		DPI0_SEL_IN_RDMA2
 	}, {
 		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1,
-		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_DPI1
+		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
+		RDMA2_SOUT_DPI1
 	}, {
 		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1,
-		DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_RDMA2
+		DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK,
+		DPI1_SEL_IN_RDMA2
 	}, {
 		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI0,
-		DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_RDMA2
+		DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK,
+		DSI0_SEL_IN_RDMA2
 	}, {
 		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1,
-		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_DSI1
+		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
+		RDMA2_SOUT_DSI1
 	}, {
 		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1,
-		DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_RDMA2
+		DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK,
+		DSI1_SEL_IN_RDMA2
 	}, {
 		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2,
-		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_DSI2
+		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
+		RDMA2_SOUT_DSI2
 	}, {
 		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2,
-		DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_RDMA2
+		DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK,
+		DSI2_SEL_IN_RDMA2
 	}, {
 		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3,
-		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_DSI3
+		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
+		RDMA2_SOUT_DSI3
 	}, {
 		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3,
-		DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_RDMA2
+		DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK,
+		DSI3_SEL_IN_RDMA2
 	}
 };
 
-- 
2.25.1


^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH v2] soc: mmsys: mediatek: add mask to mmsys routes
  2021-07-29  7:05 [PATCH v2] soc: mmsys: mediatek: add mask to mmsys routes Frank Wunderlich
@ 2021-08-04 15:17 ` Matthias Brugger
  2021-08-04 15:59   ` Aw: " Frank Wunderlich
  0 siblings, 1 reply; 3+ messages in thread
From: Matthias Brugger @ 2021-08-04 15:17 UTC (permalink / raw)
  To: Frank Wunderlich, linux-mediatek
  Cc: CK Hu, Enric Balletbo i Serra, linux-arm-kernel, linux-kernel,
	dafna.hirschfeld, Frank Wunderlich, Chun-Kuang Hu, Hsin-Yi Wang



On 29/07/2021 09:05, Frank Wunderlich wrote:
> From: CK Hu <ck.hu@mediatek.com>
> 
> SOUT has many bits and need to be cleared before set new value.
> Write only could do the clear, but for MOUT, it clears bits that
> should not be cleared. So use a mask to reset only the needed bits.
> 
> this fixes HDMI issues on MT7623/BPI-R2 since 5.13
> 
> Fixes: 440147639ac7 ("soc: mediatek: mmsys: Use an array for setting the routing registers")
> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
> Signed-off-by: CK Hu <ck.hu@mediatek.com>
> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
> Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org>

My understanding is, that this does not break mt8173 and other SoCs that use the
default routing table. Correct?

Added now to v5.14-next/soc
Thanks.

> ---
> code is taken from here (upstreamed without mask part)
> https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2345186/5
> basicly CK Hu's code so i set him as author
> ---
> v2:
> - added mask to mt8183 specific table (mask=value),
>   before val was used as mask and val itself not defined,
>   breaking display on these devices
> - as changes do not add addional code only restoring same
>   behaviour for mt8183 added reviwed-by from CK Hu from v1
> ---
>  drivers/soc/mediatek/mt8183-mmsys.h |  21 +++--
>  drivers/soc/mediatek/mtk-mmsys.c    |   7 +-
>  drivers/soc/mediatek/mtk-mmsys.h    | 133 +++++++++++++++++++---------
>  3 files changed, 112 insertions(+), 49 deletions(-)
> 
> diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h
> index 579dfc8dc8fc..9dee485807c9 100644
> --- a/drivers/soc/mediatek/mt8183-mmsys.h
> +++ b/drivers/soc/mediatek/mt8183-mmsys.h
> @@ -28,25 +28,32 @@
>  static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
>  	{
>  		DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
> -		MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L
> +		MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L,
> +		MT8183_OVL0_MOUT_EN_OVL0_2L
>  	}, {
>  		DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
> -		MT8183_DISP_OVL0_2L_MOUT_EN, MT8183_OVL0_2L_MOUT_EN_DISP_PATH0
> +		MT8183_DISP_OVL0_2L_MOUT_EN, MT8183_OVL0_2L_MOUT_EN_DISP_PATH0,
> +		MT8183_OVL0_2L_MOUT_EN_DISP_PATH0
>  	}, {
>  		DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_RDMA1,
> -		MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1
> +		MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1,
> +		MT8183_OVL1_2L_MOUT_EN_RDMA1
>  	}, {
>  		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> -		MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0
> +		MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0,
> +		MT8183_DITHER0_MOUT_IN_DSI0
>  	}, {
>  		DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
> -		MT8183_DISP_PATH0_SEL_IN, MT8183_DISP_PATH0_SEL_IN_OVL0_2L
> +		MT8183_DISP_PATH0_SEL_IN, MT8183_DISP_PATH0_SEL_IN_OVL0_2L,
> +		MT8183_DISP_PATH0_SEL_IN_OVL0_2L
>  	}, {
>  		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
> -		MT8183_DISP_DPI0_SEL_IN, MT8183_DPI0_SEL_IN_RDMA1
> +		MT8183_DISP_DPI0_SEL_IN, MT8183_DPI0_SEL_IN_RDMA1,
> +		MT8183_DPI0_SEL_IN_RDMA1
>  	}, {
>  		DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
> -		MT8183_DISP_RDMA0_SOUT_SEL_IN, MT8183_RDMA0_SOUT_COLOR0
> +		MT8183_DISP_RDMA0_SOUT_SEL_IN, MT8183_RDMA0_SOUT_COLOR0,
> +		MT8183_RDMA0_SOUT_COLOR0
>  	}
>  };
>  
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 080660ef11bf..0f949896fd06 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -68,7 +68,9 @@ void mtk_mmsys_ddp_connect(struct device *dev,
>  
>  	for (i = 0; i < mmsys->data->num_routes; i++)
>  		if (cur == routes[i].from_comp && next == routes[i].to_comp) {
> -			reg = readl_relaxed(mmsys->regs + routes[i].addr) | routes[i].val;
> +			reg = readl_relaxed(mmsys->regs + routes[i].addr);
> +			reg &= ~routes[i].mask;
> +			reg |= routes[i].val;
>  			writel_relaxed(reg, mmsys->regs + routes[i].addr);
>  		}
>  }
> @@ -85,7 +87,8 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
>  
>  	for (i = 0; i < mmsys->data->num_routes; i++)
>  		if (cur == routes[i].from_comp && next == routes[i].to_comp) {
> -			reg = readl_relaxed(mmsys->regs + routes[i].addr) & ~routes[i].val;
> +			reg = readl_relaxed(mmsys->regs + routes[i].addr);
> +			reg &= ~routes[i].mask;
>  			writel_relaxed(reg, mmsys->regs + routes[i].addr);
>  		}
>  }
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
> index a760a34e6eca..5f3e2bf0c40b 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -35,41 +35,54 @@
>  #define RDMA0_SOUT_DSI1				0x1
>  #define RDMA0_SOUT_DSI2				0x4
>  #define RDMA0_SOUT_DSI3				0x5
> +#define RDMA0_SOUT_MASK				0x7
>  #define RDMA1_SOUT_DPI0				0x2
>  #define RDMA1_SOUT_DPI1				0x3
>  #define RDMA1_SOUT_DSI1				0x1
>  #define RDMA1_SOUT_DSI2				0x4
>  #define RDMA1_SOUT_DSI3				0x5
> +#define RDMA1_SOUT_MASK				0x7
>  #define RDMA2_SOUT_DPI0				0x2
>  #define RDMA2_SOUT_DPI1				0x3
>  #define RDMA2_SOUT_DSI1				0x1
>  #define RDMA2_SOUT_DSI2				0x4
>  #define RDMA2_SOUT_DSI3				0x5
> +#define RDMA2_SOUT_MASK				0x7
>  #define DPI0_SEL_IN_RDMA1			0x1
>  #define DPI0_SEL_IN_RDMA2			0x3
> +#define DPI0_SEL_IN_MASK			0x3
>  #define DPI1_SEL_IN_RDMA1			(0x1 << 8)
>  #define DPI1_SEL_IN_RDMA2			(0x3 << 8)
> +#define DPI1_SEL_IN_MASK			(0x3 << 8)
>  #define DSI0_SEL_IN_RDMA1			0x1
>  #define DSI0_SEL_IN_RDMA2			0x4
> +#define DSI0_SEL_IN_MASK			0x7
>  #define DSI1_SEL_IN_RDMA1			0x1
>  #define DSI1_SEL_IN_RDMA2			0x4
> +#define DSI1_SEL_IN_MASK			0x7
>  #define DSI2_SEL_IN_RDMA1			(0x1 << 16)
>  #define DSI2_SEL_IN_RDMA2			(0x4 << 16)
> +#define DSI2_SEL_IN_MASK			(0x7 << 16)
>  #define DSI3_SEL_IN_RDMA1			(0x1 << 16)
>  #define DSI3_SEL_IN_RDMA2			(0x4 << 16)
> +#define DSI3_SEL_IN_MASK			(0x7 << 16)
>  #define COLOR1_SEL_IN_OVL1			0x1
>  
>  #define OVL_MOUT_EN_RDMA			0x1
>  #define BLS_TO_DSI_RDMA1_TO_DPI1		0x8
>  #define BLS_TO_DPI_RDMA1_TO_DSI			0x2
> +#define BLS_RDMA1_DSI_DPI_MASK			0xf
>  #define DSI_SEL_IN_BLS				0x0
>  #define DPI_SEL_IN_BLS				0x0
> +#define DPI_SEL_IN_MASK				0x1
>  #define DSI_SEL_IN_RDMA				0x1
> +#define DSI_SEL_IN_MASK				0x1
>  
>  struct mtk_mmsys_routes {
>  	u32 from_comp;
>  	u32 to_comp;
>  	u32 addr;
> +	u32 mask;
>  	u32 val;
>  };
>  
> @@ -91,124 +104,164 @@ struct mtk_mmsys_driver_data {
>  static const struct mtk_mmsys_routes mmsys_default_routing_table[] = {
>  	{
>  		DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0,
> -		DISP_REG_CONFIG_OUT_SEL, BLS_TO_DSI_RDMA1_TO_DPI1
> +		DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK,
> +		BLS_TO_DSI_RDMA1_TO_DPI1
>  	}, {
>  		DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0,
> -		DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_BLS
> +		DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK,
> +		DSI_SEL_IN_BLS
>  	}, {
>  		DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
> -		DISP_REG_CONFIG_OUT_SEL, BLS_TO_DPI_RDMA1_TO_DSI
> +		DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK,
> +		BLS_TO_DPI_RDMA1_TO_DSI
>  	}, {
>  		DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
> -		DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_RDMA
> +		DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK,
> +		DSI_SEL_IN_RDMA
>  	}, {
>  		DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
> -		DISP_REG_CONFIG_DPI_SEL, DPI_SEL_IN_BLS
> +		DISP_REG_CONFIG_DPI_SEL, DPI_SEL_IN_MASK,
> +		DPI_SEL_IN_BLS
>  	}, {
>  		DDP_COMPONENT_GAMMA, DDP_COMPONENT_RDMA1,
> -		DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, GAMMA_MOUT_EN_RDMA1
> +		DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, GAMMA_MOUT_EN_RDMA1,
> +		GAMMA_MOUT_EN_RDMA1
>  	}, {
>  		DDP_COMPONENT_OD0, DDP_COMPONENT_RDMA0,
> -		DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD_MOUT_EN_RDMA0
> +		DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD_MOUT_EN_RDMA0,
> +		OD_MOUT_EN_RDMA0
>  	}, {
>  		DDP_COMPONENT_OD1, DDP_COMPONENT_RDMA1,
> -		DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD1_MOUT_EN_RDMA1
> +		DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD1_MOUT_EN_RDMA1,
> +		OD1_MOUT_EN_RDMA1
>  	}, {
>  		DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
> -		DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0
> +		DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
> +		OVL0_MOUT_EN_COLOR0
>  	}, {
>  		DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
> -		DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0
> +		DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0,
> +		COLOR0_SEL_IN_OVL0
>  	}, {
>  		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> -		DISP_REG_CONFIG_DISP_OVL_MOUT_EN, OVL_MOUT_EN_RDMA
> +		DISP_REG_CONFIG_DISP_OVL_MOUT_EN, OVL_MOUT_EN_RDMA,
> +		OVL_MOUT_EN_RDMA
>  	}, {
>  		DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
> -		DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, OVL1_MOUT_EN_COLOR1
> +		DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, OVL1_MOUT_EN_COLOR1,
> +		OVL1_MOUT_EN_COLOR1
>  	}, {
>  		DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
> -		DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1
> +		DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1,
> +		COLOR1_SEL_IN_OVL1
>  	}, {
>  		DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI0,
> -		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_DPI0
> +		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
> +		RDMA0_SOUT_DPI0
>  	}, {
>  		DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI1,
> -		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_DPI1
> +		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
> +		RDMA0_SOUT_DPI1
>  	}, {
>  		DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI1,
> -		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_DSI1
> +		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
> +		RDMA0_SOUT_DSI1
>  	}, {
>  		DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI2,
> -		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_DSI2
> +		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
> +		RDMA0_SOUT_DSI2
>  	}, {
>  		DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI3,
> -		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_DSI3
> +		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
> +		RDMA0_SOUT_DSI3
>  	}, {
>  		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
> -		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_DPI0
> +		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
> +		RDMA1_SOUT_DPI0
>  	}, {
>  		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
> -		DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_RDMA1
> +		DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK,
> +		DPI0_SEL_IN_RDMA1
>  	}, {
>  		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1,
> -		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_DPI1
> +		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
> +		RDMA1_SOUT_DPI1
>  	}, {
>  		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1,
> -		DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_RDMA1
> +		DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK,
> +		DPI1_SEL_IN_RDMA1
>  	}, {
>  		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI0,
> -		DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_RDMA1
> +		DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK,
> +		DSI0_SEL_IN_RDMA1
>  	}, {
>  		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1,
> -		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_DSI1
> +		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
> +		RDMA1_SOUT_DSI1
>  	}, {
>  		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1,
> -		DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_RDMA1
> +		DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK,
> +		DSI1_SEL_IN_RDMA1
>  	}, {
>  		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2,
> -		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_DSI2
> +		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
> +		RDMA1_SOUT_DSI2
>  	}, {
>  		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2,
> -		DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_RDMA1
> +		DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK,
> +		DSI2_SEL_IN_RDMA1
>  	}, {
>  		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3,
> -		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_DSI3
> +		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
> +		RDMA1_SOUT_DSI3
>  	}, {
>  		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3,
> -		DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_RDMA1
> +		DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK,
> +		DSI3_SEL_IN_RDMA1
>  	}, {
>  		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0,
> -		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_DPI0
> +		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
> +		RDMA2_SOUT_DPI0
>  	}, {
>  		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0,
> -		DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_RDMA2
> +		DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK,
> +		DPI0_SEL_IN_RDMA2
>  	}, {
>  		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1,
> -		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_DPI1
> +		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
> +		RDMA2_SOUT_DPI1
>  	}, {
>  		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1,
> -		DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_RDMA2
> +		DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK,
> +		DPI1_SEL_IN_RDMA2
>  	}, {
>  		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI0,
> -		DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_RDMA2
> +		DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK,
> +		DSI0_SEL_IN_RDMA2
>  	}, {
>  		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1,
> -		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_DSI1
> +		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
> +		RDMA2_SOUT_DSI1
>  	}, {
>  		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1,
> -		DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_RDMA2
> +		DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK,
> +		DSI1_SEL_IN_RDMA2
>  	}, {
>  		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2,
> -		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_DSI2
> +		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
> +		RDMA2_SOUT_DSI2
>  	}, {
>  		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2,
> -		DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_RDMA2
> +		DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK,
> +		DSI2_SEL_IN_RDMA2
>  	}, {
>  		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3,
> -		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_DSI3
> +		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
> +		RDMA2_SOUT_DSI3
>  	}, {
>  		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3,
> -		DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_RDMA2
> +		DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK,
> +		DSI3_SEL_IN_RDMA2
>  	}
>  };
>  
> 

^ permalink raw reply	[flat|nested] 3+ messages in thread

* Aw: Re: [PATCH v2] soc: mmsys: mediatek: add mask to mmsys routes
  2021-08-04 15:17 ` Matthias Brugger
@ 2021-08-04 15:59   ` Frank Wunderlich
  0 siblings, 0 replies; 3+ messages in thread
From: Frank Wunderlich @ 2021-08-04 15:59 UTC (permalink / raw)
  To: Matthias Brugger
  Cc: Frank Wunderlich, linux-mediatek, CK Hu, Enric Balletbo i Serra,
	linux-arm-kernel, linux-kernel, dafna.hirschfeld, Chun-Kuang Hu,
	Hsin-Yi Wang

Hi,

> Gesendet: Mittwoch, 04. August 2021 um 17:17 Uhr
> Von: "Matthias Brugger" <matthias.bgg@gmail.com>

> My understanding is, that this does not break mt8173 and other SoCs that use the
> default routing table. Correct?

i took the mask values from CK Hu's Patch, mt7623 uses this table and with it hdmi works again (was broken by the array-commit). I'm not sure on which devices Chun-Kuang has tested it, he only suggests to add the mask again from his commit to fix mt7623.

https://patchwork.kernel.org/project/linux-mediatek/patch/20210710132431.265985-1-linux@fw-web.de/#24335233

I can only test on mt7623/BPI-R2...

there is a new patchset for mt8192 which adds a new routing-table, which needs to be extended with mask values (without it wil not work, but maybe duplicate values may work):

https://patchwork.kernel.org/project/linux-mediatek/patch/1627894773-23872-3-git-send-email-yongqiang.niu@mediatek.com/

regards Frank

> Added now to v5.14-next/soc
> Thanks.

Thanks too

^ permalink raw reply	[flat|nested] 3+ messages in thread

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2021-07-29  7:05 [PATCH v2] soc: mmsys: mediatek: add mask to mmsys routes Frank Wunderlich
2021-08-04 15:17 ` Matthias Brugger
2021-08-04 15:59   ` Aw: " Frank Wunderlich

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