From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7B414682 for ; Sun, 25 Sep 2022 23:30:11 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 770B9C433D7 for ; Sun, 25 Sep 2022 23:30:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1664148611; bh=0dkLfkpN4bl6+XUgOrEzocRDFO2GLiA4mip+arTaoJU=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=QQSkMZYZUkGzP15UheuDVf6q6ELa7I+MaMsKTleqTBELVuJF0HsUlZ0E+QO7dCAUZ SdzVfxXScTZd1iY4dT/g6SJbI3QZr0hQqMPLyvz3dONRCiXxbOhUhZe5sYfnXx4rF3 PWGrHS4tdqFLkX1p9Q+o10b+/J4iusUrPzIjqep3G8zGYDAGnkOyrRyxgk/dd9aI95 tuae4uV9bxFs8WiYaPmfq3rkuDFoqwAvMBDNf9VXCmurtDDN/d2jWF/5auc7ORZHGp BtDw2e9JiYNSK+msY4nW0ePXf6zdA4g7JfcX5uAfPL8QoYd5SfHzsi30IWORNE/6Px Y0ELg+0zECppw== Received: by mail-oi1-f170.google.com with SMTP id m130so6419938oif.6 for ; Sun, 25 Sep 2022 16:30:11 -0700 (PDT) X-Gm-Message-State: ACrzQf0l26mGHMFnPxxrwbZT5goPhm8klXeJlyHMQ1/ZfMwuM+8aT3B/ PJnp4X/7aw+Pi7hnVPL7hnXvG269WHIvlLQnXyo= X-Google-Smtp-Source: AMsMyM78H8xRByyG0Kx8aSGOYIjP57Juz7vq8m3nhivoMNVDUsp0tW0/ImKxj4XFvVU/79/z7jAP6Vux6xHUVeayUiU= X-Received: by 2002:a05:6808:151f:b0:350:1b5e:2380 with SMTP id u31-20020a056808151f00b003501b5e2380mr13923041oiw.112.1664148610641; Sun, 25 Sep 2022 16:30:10 -0700 (PDT) Precedence: bulk X-Mailing-List: llvm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20220925175356.681-1-jszhang@kernel.org> <20220925175356.681-5-jszhang@kernel.org> In-Reply-To: <20220925175356.681-5-jszhang@kernel.org> From: Guo Ren Date: Mon, 26 Sep 2022 07:29:58 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 4/4] riscv: entry: consolidate general regs saving into save_gp To: Jisheng Zhang Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Nathan Chancellor , Nick Desaulniers , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev Content-Type: text/plain; charset="UTF-8" Acked-by: Guo Ren For the save & restore pair, I also suggest adding restore_gp. On Mon, Sep 26, 2022 at 2:03 AM Jisheng Zhang wrote: > > Consolidate the saving GPs(except sp and tp into save_gp macro. > No functional change. > > Signed-off-by: Jisheng Zhang > --- > arch/riscv/kernel/entry.S | 85 ++++++++++++++------------------------- > 1 file changed, 31 insertions(+), 54 deletions(-) > > diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S > index 442d93beffcf..04e11d257ad6 100644 > --- a/arch/riscv/kernel/entry.S > +++ b/arch/riscv/kernel/entry.S > @@ -14,31 +14,8 @@ > #include > #include > > -ENTRY(handle_exception) > - /* > - * If coming from userspace, preserve the user thread pointer and load > - * the kernel thread pointer. If we came from the kernel, the scratch > - * register will contain 0, and we should continue on the current TP. > - */ > - csrrw tp, CSR_SCRATCH, tp > - bnez tp, _save_context > - > -_restore_kernel_tpsp: > - csrr tp, CSR_SCRATCH > - REG_S sp, TASK_TI_KERNEL_SP(tp) > - > -#ifdef CONFIG_VMAP_STACK > - addi sp, sp, -(PT_SIZE_ON_STACK) > - srli sp, sp, THREAD_SHIFT > - andi sp, sp, 0x1 > - bnez sp, handle_kernel_stack_overflow > - REG_L sp, TASK_TI_KERNEL_SP(tp) > -#endif > - > -_save_context: > - REG_S sp, TASK_TI_USER_SP(tp) > - REG_L sp, TASK_TI_KERNEL_SP(tp) > - addi sp, sp, -(PT_SIZE_ON_STACK) > + /* save all GPs except sp and tp */ > + .macro save_gp > REG_S x1, PT_RA(sp) > REG_S x3, PT_GP(sp) > REG_S x5, PT_T0(sp) > @@ -68,6 +45,34 @@ _save_context: > REG_S x29, PT_T4(sp) > REG_S x30, PT_T5(sp) > REG_S x31, PT_T6(sp) > + .endm > + > +ENTRY(handle_exception) > + /* > + * If coming from userspace, preserve the user thread pointer and load > + * the kernel thread pointer. If we came from the kernel, the scratch > + * register will contain 0, and we should continue on the current TP. > + */ > + csrrw tp, CSR_SCRATCH, tp > + bnez tp, _save_context > + > +_restore_kernel_tpsp: > + csrr tp, CSR_SCRATCH > + REG_S sp, TASK_TI_KERNEL_SP(tp) > + > +#ifdef CONFIG_VMAP_STACK > + addi sp, sp, -(PT_SIZE_ON_STACK) > + srli sp, sp, THREAD_SHIFT > + andi sp, sp, 0x1 > + bnez sp, handle_kernel_stack_overflow > + REG_L sp, TASK_TI_KERNEL_SP(tp) > +#endif > + > +_save_context: > + REG_S sp, TASK_TI_USER_SP(tp) > + REG_L sp, TASK_TI_KERNEL_SP(tp) > + addi sp, sp, -(PT_SIZE_ON_STACK) > + save_gp > > /* > * Disable user-mode memory access as it should only be set in the > @@ -234,35 +239,7 @@ ENTRY(handle_kernel_stack_overflow) > addi sp, sp, -(PT_SIZE_ON_STACK) > > //save context to overflow stack > - REG_S x1, PT_RA(sp) > - REG_S x3, PT_GP(sp) > - REG_S x5, PT_T0(sp) > - REG_S x6, PT_T1(sp) > - REG_S x7, PT_T2(sp) > - REG_S x8, PT_S0(sp) > - REG_S x9, PT_S1(sp) > - REG_S x10, PT_A0(sp) > - REG_S x11, PT_A1(sp) > - REG_S x12, PT_A2(sp) > - REG_S x13, PT_A3(sp) > - REG_S x14, PT_A4(sp) > - REG_S x15, PT_A5(sp) > - REG_S x16, PT_A6(sp) > - REG_S x17, PT_A7(sp) > - REG_S x18, PT_S2(sp) > - REG_S x19, PT_S3(sp) > - REG_S x20, PT_S4(sp) > - REG_S x21, PT_S5(sp) > - REG_S x22, PT_S6(sp) > - REG_S x23, PT_S7(sp) > - REG_S x24, PT_S8(sp) > - REG_S x25, PT_S9(sp) > - REG_S x26, PT_S10(sp) > - REG_S x27, PT_S11(sp) > - REG_S x28, PT_T3(sp) > - REG_S x29, PT_T4(sp) > - REG_S x30, PT_T5(sp) > - REG_S x31, PT_T6(sp) > + save_gp > > REG_L s0, TASK_TI_KERNEL_SP(tp) > csrr s1, CSR_STATUS > -- > 2.34.1 > -- Best Regards Guo Ren