From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-oi1-f178.google.com (mail-oi1-f178.google.com [209.85.167.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D90B20F3 for ; Wed, 31 May 2023 06:25:57 +0000 (UTC) Received: by mail-oi1-f178.google.com with SMTP id 5614622812f47-39a53c7648fso89840b6e.1 for ; Tue, 30 May 2023 23:25:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685514356; x=1688106356; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date:from:to :cc:subject:date:message-id:reply-to; bh=6QEemah19M6O9zXMW59Hl4eoCOU3nOcUSmXPFvc40qY=; b=yfU72+a+V2j1RGJPAmrckG8hM7WDnXqiHNyDYmGNLaKUCMEP4XxwviwX+agCGFrcLP Yo8vfNa08n1FVaMu0X1PY/t9b1Ubsjk9QaMuY0vEHxiWyShKpqdddJ+KaVP3vc0epElt YfyhQnGsE3WgjqORPELcNGKiQF65PqC+1I3LqsMMk/YxvkCcp8UuGfrg4sDBCA+cYpeJ 3+BMapGTMNFXdVhYOmuwDq/Aj85/RlK5TF+VnOqL1tDxpxpZbyPsTiw8dlC6Bam3Wye7 xTR11c4SfSSwIbAZMFAPU3SjiNn3/3LC8RuWdPt9dxLt73JV1ewK8lUEFVVh6JqOhsiY thfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685514356; x=1688106356; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=6QEemah19M6O9zXMW59Hl4eoCOU3nOcUSmXPFvc40qY=; b=i1+g4st35i46VBFeLGhTuiIEAa+bsB0XqIwO2rKimNh5d2pggoUGb2LN2qH2D0Jl1U C9iLlbopj4Qnn2qaIggtAkzWlpwCee5q4a+7Q/zTeIHoAX/GxiB+RE3ECtuSUwYx7efW sPyqmwyLYtJCsnWJiIRutY9Sc+IMmdNrC9jh4CMkahN2ruyhaDuYWDQcDdwQuiQdepfR Rc6gVs02JpmuyXTkzJln44ZQxsjffv1OS9Tj3PvZboZFLtv/EWMrUP48KCABD6bfkUAf TxcHT9L0KPO3L9OZ/drGiAAuIu/29Y0lPMYwMJcd06KH0J5F/s1tEJ0KUkOP5MwIj2Q7 WAEg== X-Gm-Message-State: AC+VfDxvbXcrO6yXIGVTiab/Anqz/Wu044Eqeeg/45Sb1ev4iSub8Vb7 XKf1VHEt6Vhpri6VfbWBYRGi X-Google-Smtp-Source: ACHHUZ7UhgIzbO0+5ARVJsxpkjyAwkwawoZkIijG0DTJ0OpOoUf3tpw7dMYdvCkbhrqK0+T6PV9O+Q== X-Received: by 2002:a05:6808:8c2:b0:398:36a0:d42 with SMTP id k2-20020a05680808c200b0039836a00d42mr2894012oij.39.1685514356188; Tue, 30 May 2023 23:25:56 -0700 (PDT) Received: from thinkpad ([117.217.186.173]) by smtp.gmail.com with ESMTPSA id w12-20020a170902e88c00b001aaf370b1c7sm404309plg.278.2023.05.30.23.25.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 23:25:55 -0700 (PDT) Date: Wed, 31 May 2023 11:55:50 +0530 From: Manivannan Sadhasivam To: Loic Poulain Cc: mhi@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, quic_krichai@quicinc.com Subject: Re: [PATCH] bus: mhi: host: pci_generic: Add support for IP_SW0 channels Message-ID: <20230531062550.GA7968@thinkpad> References: <20230519135803.13850-1-manivannan.sadhasivam@linaro.org> Precedence: bulk X-Mailing-List: mhi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Sun, May 21, 2023 at 08:27:45PM +0200, Loic Poulain wrote: > On Fri, 19 May 2023 at 15:58, Manivannan Sadhasivam > wrote: > > > > IP_SW0 channels are used to transfer data over the networking interface > > between MHI endpoint and the host. Define the channels in the MHI v1 > > channel config along with dedicated event rings. > > > > Signed-off-by: Manivannan Sadhasivam > > Assuming we can extend the number of event rings (and dedicated irqs) > without hitting any hardware limitation on the device side? > Not all endpoints support IP_SW0 channels. Only a few devices that intend to transfer non-IP data payload supports it and those should take care of the requirements. - Mani > Reviewed-by: Loic Poulain > > > > > --- > > drivers/bus/mhi/host/pci_generic.c | 26 ++++++++++++++++++++++---- > > 1 file changed, 22 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c > > index db0a0b062d8e..70e37c490150 100644 > > --- a/drivers/bus/mhi/host/pci_generic.c > > +++ b/drivers/bus/mhi/host/pci_generic.c > > @@ -212,6 +212,19 @@ struct mhi_pci_dev_info { > > .offload_channel = false, \ > > } > > > > +#define MHI_EVENT_CONFIG_SW_DATA(ev_ring, el_count) \ > > + { \ > > + .num_elements = el_count, \ > > + .irq_moderation_ms = 0, \ > > + .irq = (ev_ring) + 1, \ > > + .priority = 1, \ > > + .mode = MHI_DB_BRST_DISABLE, \ > > + .data_type = MHI_ER_DATA, \ > > + .hardware_event = false, \ > > + .client_managed = false, \ > > + .offload_channel = false, \ > > + } > > + > > #define MHI_EVENT_CONFIG_HW_DATA(ev_ring, el_count, ch_num) \ > > { \ > > .num_elements = el_count, \ > > @@ -237,8 +250,10 @@ static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { > > MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(21, "IPCR", 8, 0), > > MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), > > MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), > > - MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 2), > > - MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 3), > > + MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 64, 2), > > + MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 64, 3), > > + MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 4), > > + MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 5), > > }; > > > > static struct mhi_event_config modem_qcom_v1_mhi_events[] = { > > @@ -246,9 +261,12 @@ static struct mhi_event_config modem_qcom_v1_mhi_events[] = { > > MHI_EVENT_CONFIG_CTRL(0, 64), > > /* DIAG dedicated event ring */ > > MHI_EVENT_CONFIG_DATA(1, 128), > > + /* Software channels dedicated event ring */ > > + MHI_EVENT_CONFIG_SW_DATA(2, 64), > > + MHI_EVENT_CONFIG_SW_DATA(3, 64), > > /* Hardware channels request dedicated hardware event rings */ > > - MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), > > - MHI_EVENT_CONFIG_HW_DATA(3, 2048, 101) > > + MHI_EVENT_CONFIG_HW_DATA(4, 1024, 100), > > + MHI_EVENT_CONFIG_HW_DATA(5, 2048, 101) > > }; > > > > static const struct mhi_controller_config modem_qcom_v1_mhiv_config = { > > -- > > 2.25.1 > > -- மணிவண்ணன் சதாசிவம்