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[83.9.1.37]) by smtp.gmail.com with ESMTPSA id o7-20020a05651238a700b004d887e0e9edsm2439673lft.168.2023.04.04.11.34.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 04 Apr 2023 11:34:25 -0700 (PDT) Message-ID: <0d2f0792-c7dd-7cdc-3c1c-454f445405aa@linaro.org> Date: Tue, 4 Apr 2023 20:34:23 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.1 Subject: Re: [PATCH v3 2/3] arm64: dts: qcom: sc8280xp: Add ethernet nodes Content-Language: en-US To: Andrew Halaney , linux-kernel@vger.kernel.org Cc: agross@kernel.org, andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, richardcochran@gmail.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, netdev@vger.kernel.org, bmasney@redhat.com, echanude@redhat.com, ncai@quicinc.com, jsuraj@qti.qualcomm.com, hisunil@quicinc.com References: <20230331215804.783439-1-ahalaney@redhat.com> <20230331215804.783439-3-ahalaney@redhat.com> From: Konrad Dybcio In-Reply-To: <20230331215804.783439-3-ahalaney@redhat.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On 31.03.2023 23:58, Andrew Halaney wrote: > This platform has 2 MACs integrated in it, go ahead and describe them. > > Signed-off-by: Andrew Halaney > --- > > Changes since v2: > * Fix spacing (Konrad) > > Changes since v1: > * None > > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 59 ++++++++++++++++++++++++++ > 1 file changed, 59 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > index 42bfa9fa5b96..f28ea86b128d 100644 > --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > @@ -761,6 +761,65 @@ soc: soc@0 { > ranges = <0 0 0 0 0x10 0>; > dma-ranges = <0 0 0 0 0x10 0>; > > + ethernet0: ethernet@20000 { > + compatible = "qcom,sc8280xp-ethqos"; > + reg = <0x0 0x00020000 0x0 0x10000>, > + <0x0 0x00036000 0x0 0x100>; > + reg-names = "stmmaceth", "rgmii"; > + > + clocks = <&gcc GCC_EMAC0_AXI_CLK>, > + <&gcc GCC_EMAC0_SLV_AHB_CLK>, > + <&gcc GCC_EMAC0_PTP_CLK>, > + <&gcc GCC_EMAC0_RGMII_CLK>; > + clock-names = "stmmaceth", > + "pclk", > + "ptp_ref", > + "rgmii"; > + > + interrupts = , > + ; > + interrupt-names = "macirq", "eth_lpi"; > + iommus = <&apps_smmu 0x4c0 0xf>; > + power-domains = <&gcc EMAC_0_GDSC>; > + > + snps,tso; > + snps,pbl = <32>; > + rx-fifo-depth = <4096>; > + tx-fifo-depth = <4096>; > + > + status = "disabled"; > + }; > + > + ethernet1: ethernet@23000000 { Nodes under /soc should be ordered by their unit address, so in this case it belongs after dispcc1: clock-controller@.. With that fixed: Reviewed-by: Konrad Dybcio Konrad > + compatible = "qcom,sc8280xp-ethqos"; > + reg = <0x0 0x23000000 0x0 0x10000>, > + <0x0 0x23016000 0x0 0x100>; > + reg-names = "stmmaceth", "rgmii"; > + > + clocks = <&gcc GCC_EMAC1_AXI_CLK>, > + <&gcc GCC_EMAC1_SLV_AHB_CLK>, > + <&gcc GCC_EMAC1_PTP_CLK>, > + <&gcc GCC_EMAC1_RGMII_CLK>; > + clock-names = "stmmaceth", > + "pclk", > + "ptp_ref", > + "rgmii"; > + > + interrupts = , > + ; > + interrupt-names = "macirq", "eth_lpi"; > + > + iommus = <&apps_smmu 0x40 0xf>; > + power-domains = <&gcc EMAC_1_GDSC>; > + > + snps,tso; > + snps,pbl = <32>; > + rx-fifo-depth = <4096>; > + tx-fifo-depth = <4096>; > + > + status = "disabled"; > + }; > + > gcc: clock-controller@100000 { > compatible = "qcom,gcc-sc8280xp"; > reg = <0x0 0x00100000 0x0 0x1f0000>;