From: Sean Anderson <sean.anderson@seco.com>
To: "Russell King (Oracle)" <linux@armlinux.org.uk>
Cc: Andrew Lunn <andrew@lunn.ch>,
Heiner Kallweit <hkallweit1@gmail.com>,
netdev@vger.kernel.org, Vladimir Oltean <olteanv@gmail.com>,
Eric Dumazet <edumazet@google.com>,
Paolo Abeni <pabeni@redhat.com>,
linux-kernel@vger.kernel.org, Jakub Kicinski <kuba@kernel.org>,
Tim Harvey <tharvey@gateworks.com>,
"David S . Miller" <davem@davemloft.net>
Subject: Re: [PATCH net v2 2/2] phy: aquantia: Determine rate adaptation support from registers
Date: Tue, 29 Nov 2022 11:29:39 -0500 [thread overview]
Message-ID: <10c0545d-d9aa-8d85-e3ba-ee739cb126ef@seco.com> (raw)
In-Reply-To: <Y4Ywh+0p8tfTMt0f@shell.armlinux.org.uk>
On 11/29/22 11:17, Russell King (Oracle) wrote:
> On Tue, Nov 29, 2022 at 10:56:56AM -0500, Sean Anderson wrote:
>> On 11/28/22 19:42, Russell King (Oracle) wrote:
>> > On Mon, Nov 28, 2022 at 07:21:56PM -0500, Sean Anderson wrote:
>> >> On 11/28/22 18:22, Russell King (Oracle) wrote:
>> >> > This doesn't make any sense. priv->supported_speeds is the set of speeds
>> >> > read from the PMAPMD. The only bits that are valid for this are the
>> >> > MDIO_PMA_SPEED_* definitions, but teh above switch makes use of the
>> >> > MDIO_PCS_SPEED_* definitions. To see why this is wrong, look at these
>> >> > two definitions:
>> >> >
>> >> > #define MDIO_PMA_SPEED_10 0x0040 /* 10M capable */
>> >> > #define MDIO_PCS_SPEED_2_5G 0x0040 /* 2.5G capable */
>> >> >
>> >> > Note that they are the same value, yet above, you're testing for bit 6
>> >> > being clear effectively for both 10M and 2.5G speeds. I suspect this
>> >> > is *not* what you want.
>> >> >
>> >> > MDIO_PMA_SPEED_* are only valid for the PMAPMD MMD (MMD 1).
>> >> > MDIO_PCS_SPEED_* are only valid for the PCS MMD (MMD 3).
>> >>
>> >> Ugh. I almost noticed this from the register naming...
>> >>
>> >> Part of the problem is that all the defines are right next to each other
>> >> with no indication of what you just described.
>> >
>> > That's because they all refer to the speed register which is at the same
>> > address, but for some reason the 802.3 committees decided to make the
>> > register bits mean different things depending on the MMD. That's why the
>> > definition states the MMD name in it.
>>
>> Well, then it's really a different register per MMD (and therefore the
>> definitions should be better separated). Grouping them together implies
>> that they share bits, when they do not (except for the 10G bit).
>
> What about bits that are shared amongst the different registers.
> Should we have multiple definitions for the link status bit in _all_
> the different MMDs, despite it being the same across all status 1
> registers?
No, but for registers which are 95% difference we should at least separate
them and add a comment.
> Clause 45 is quite a trainwreck when it comes to these register
> definitions.
Maybe they should have randomized the bit orders in the first place to discourage this sort of thing :)
> As I've stated, there is a pattern to the naming. Understand it,
> and it isn't confusing.
>
I don't have a problem with the naming, just the organization of the
source file.
--Sean
--Sean
next prev parent reply other threads:[~2022-11-29 16:29 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-28 19:54 [PATCH net v2 1/2] net: phy: Move/rename phylink_interface_max_speed Sean Anderson
2022-11-28 19:54 ` [PATCH net v2 2/2] phy: aquantia: Determine rate adaptation support from registers Sean Anderson
2022-11-28 23:22 ` Russell King (Oracle)
2022-11-29 0:21 ` Sean Anderson
2022-11-29 0:42 ` Russell King (Oracle)
2022-11-29 15:56 ` Sean Anderson
2022-11-29 16:17 ` Russell King (Oracle)
2022-11-29 16:29 ` Sean Anderson [this message]
2022-11-29 16:46 ` Russell King (Oracle)
2022-11-29 16:57 ` Sean Anderson
2022-11-29 13:39 ` Andrew Lunn
2022-11-29 13:46 ` Russell King (Oracle)
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