From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.4 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,URIBL_SBL,URIBL_SBL_A, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9D8DC4740A for ; Mon, 9 Sep 2019 16:05:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 81A3321920 for ; Mon, 9 Sep 2019 16:05:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=cloudbear.ru header.i=@cloudbear.ru header.b="lrIRuQft" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726533AbfIIQF2 (ORCPT ); Mon, 9 Sep 2019 12:05:28 -0400 Received: from forward105p.mail.yandex.net ([77.88.28.108]:59414 "EHLO forward105p.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725263AbfIIQC1 (ORCPT ); Mon, 9 Sep 2019 12:02:27 -0400 Received: from mxback29j.mail.yandex.net (mxback29j.mail.yandex.net [IPv6:2a02:6b8:0:1619::229]) by forward105p.mail.yandex.net (Yandex) with ESMTP id B982D4D40FFA; Mon, 9 Sep 2019 19:02:23 +0300 (MSK) Received: from smtp1j.mail.yandex.net (smtp1j.mail.yandex.net [2a02:6b8:0:801::ab]) by mxback29j.mail.yandex.net (nwsmtp/Yandex) with ESMTP id vE1n8F662e-2M4WllRU; Mon, 09 Sep 2019 19:02:23 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloudbear.ru; s=mail; t=1568044943; bh=k8swhfH/56jurkc7C5cLy1ftu0/fKHmRA39ehTChfM8=; h=In-Reply-To:Subject:To:From:Cc:References:Date:Message-Id; b=lrIRuQftEvMD+52NO5XWMRrxWWcE5ZPF/bDQt0/alUTAUNZnO2DZ6SWlqPcyuF3MK o054khqRt+cNWYlM1h0FcI/xcdyMrypyQ0Lfg0ZC5aJqFpzouhtsRhFRzq7sfmLMn9 nt14eq+D8kS7YYCI6vVEh8S70lSOIZ+fPcjAbGOQ= Authentication-Results: mxback29j.mail.yandex.net; dkim=pass header.i=@cloudbear.ru Received: by smtp1j.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id 2w9xv2RtrL-2L7KhgjB; Mon, 09 Sep 2019 19:02:22 +0300 (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (Client certificate not present) From: Vitaly Gaiduk To: davem@davemloft.net, robh+dt@kernel.org, f.fainelli@gmail.com Cc: Vitaly Gaiduk , Andrew Lunn , Heiner Kallweit , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3] net: phy: dp83867: Add SGMII mode type switching Date: Mon, 9 Sep 2019 19:02:16 +0300 Message-Id: <1568044937-12526-1-git-send-email-vitaly.gaiduk@cloudbear.ru> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1568026945-3857-1-git-send-email-vitaly.gaiduk@cloudbear.ru> References: <1568026945-3857-1-git-send-email-vitaly.gaiduk@cloudbear.ru> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch adds ability to switch beetween two PHY SGMII modes. Some hardware, for example, FPGA IP designs may use 6-wire mode which enables differential SGMII clock to MAC. Signed-off-by: Vitaly Gaiduk --- Changes in v3: - Fixed retaining DP83867_SGMII_TYPE bit drivers/net/phy/dp83867.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index 1f1ecee..37fceaf 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -37,6 +37,7 @@ #define DP83867_STRAP_STS2 0x006f #define DP83867_RGMIIDCTL 0x0086 #define DP83867_IO_MUX_CFG 0x0170 +#define DP83867_SGMIICTL 0x00D3 #define DP83867_10M_SGMII_CFG 0x016F #define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7) @@ -61,6 +62,9 @@ #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1) #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0) +/* SGMIICTL bits */ +#define DP83867_SGMII_TYPE BIT(14) + /* STRAP_STS1 bits */ #define DP83867_STRAP_STS1_RESERVED BIT(11) @@ -109,6 +113,7 @@ struct dp83867_private { bool rxctrl_strap_quirk; bool set_clk_output; u32 clk_output_sel; + bool sgmii_ref_clk_en; }; static int dp83867_ack_interrupt(struct phy_device *phydev) @@ -197,6 +202,9 @@ static int dp83867_of_init(struct phy_device *phydev) dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node, "ti,dp83867-rxctrl-strap-quirk"); + dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node, + "ti,sgmii-ref-clock-output-enable"); + /* Existing behavior was to use default pin strapping delay in rgmii * mode, but rgmii should have meant no delay. Warn existing users. */ @@ -389,6 +397,17 @@ static int dp83867_config_init(struct phy_device *phydev) if (ret) return ret; + + val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL); + /* SGMII type is set to 4-wire mode by default. + * If we place appropriate property in dts (see above) + * switch on 6-wire mode. + */ + if (dp83867->sgmii_ref_clk_en) + val |= DP83867_SGMII_TYPE; + else + val &= ~DP83867_SGMII_TYPE; + phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val); } /* Enable Interrupt output INT_OE in CFG3 register */ -- 2.7.4