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From: Harini Katakam <harini.katakam@xilinx.com>
To: nicolas.ferre@microchip.com, davem@davemloft.net,
	claudiu.beznea@microchip.com
Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
	michal.simek@xilinx.com, harinikatakamlinux@gmail.com,
	harini.katakam@xilinx.com
Subject: [PATCH 0/2] TSO bug fixes
Date: Fri, 31 Jan 2020 15:57:33 +0530	[thread overview]
Message-ID: <1580466455-27288-1-git-send-email-harini.katakam@xilinx.com> (raw)

An IP errata was recently discovered when testing TSO enabled versions
with perf test tools where a false amba error is reported by the IP.
Some ways to reproduce would be to use iperf or applications with payload
descriptor sizes very close to 16K. Once the error is observed TXERR (or
bit 6 of ISR) will be constantly triggered leading to a series of tx path
error handling and clean up. Workaround the same by limiting this size to
0x3FC0 as recommended by Cadence. There was no performance impact on 1G
system that I tested with.

Note on patch 1: The alignment code may be unused but leaving it there
in case anyone is using UFO.

Harini Katakam (2):
  net: macb: Remove unnecessary alignment check for TSO
  net: macb: Limit maximum GEM TX length in TSO

 drivers/net/ethernet/cadence/macb_main.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

-- 
2.7.4


             reply	other threads:[~2020-01-31 10:27 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-31 10:27 Harini Katakam [this message]
2020-01-31 10:27 ` [PATCH 1/2] net: macb: Remove unnecessary alignment check for TSO Harini Katakam
2020-01-31 10:27 ` [PATCH 2/2] net: macb: Limit maximum GEM TX length in TSO Harini Katakam
2020-01-31 14:57   ` Claudiu.Beznea
2020-01-31 16:14     ` Harini Katakam
2020-02-01 19:30 ` [PATCH 0/2] TSO bug fixes Jakub Kicinski

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