From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E378C4338F for ; Fri, 30 Jul 2021 03:18:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EC49861050 for ; Fri, 30 Jul 2021 03:18:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235572AbhG3DSH (ORCPT ); Thu, 29 Jul 2021 23:18:07 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:7902 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234520AbhG3DSG (ORCPT ); Thu, 29 Jul 2021 23:18:06 -0400 Received: from dggemv704-chm.china.huawei.com (unknown [172.30.72.53]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4GbXYf2wNmz824G; Fri, 30 Jul 2021 11:14:14 +0800 (CST) Received: from dggemi759-chm.china.huawei.com (10.1.198.145) by dggemv704-chm.china.huawei.com (10.3.19.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2176.2; Fri, 30 Jul 2021 11:18:00 +0800 Received: from localhost.localdomain (10.67.165.24) by dggemi759-chm.china.huawei.com (10.1.198.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Fri, 30 Jul 2021 11:18:00 +0800 From: Guangbin Huang To: , , , , , , , CC: , , , , Subject: [PATCH net-next 2/4] io: add function to flush the write combine buffer to device immediately Date: Fri, 30 Jul 2021 11:14:22 +0800 Message-ID: <1627614864-50824-3-git-send-email-huangguangbin2@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1627614864-50824-1-git-send-email-huangguangbin2@huawei.com> References: <1627614864-50824-1-git-send-email-huangguangbin2@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.165.24] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggemi759-chm.china.huawei.com (10.1.198.145) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Xiongfeng Wang Device registers can be mapped as write-combine type. In this case, data are not written into the device immediately. They are temporarily stored in the write combine buffer and written into the device when the buffer is full. But in some situation, we need to flush the write combine buffer to device immediately for better performance. So we add a general function called 'flush_wc_write()'. We use DGH instruction to implement this function for ARM64. Signed-off-by: Xiongfeng Wang Signed-off-by: Guangbin Huang --- arch/arm64/include/asm/io.h | 2 ++ include/linux/io.h | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h index 7fd836bea7eb..5315d023b2dd 100644 --- a/arch/arm64/include/asm/io.h +++ b/arch/arm64/include/asm/io.h @@ -112,6 +112,8 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) #define __iowmb() dma_wmb() #define __iomb() dma_mb() +#define flush_wc_write() dgh() + /* * Relaxed I/O memory access primitives. These follow the Device memory * ordering rules but do not guarantee any ordering relative to Normal memory diff --git a/include/linux/io.h b/include/linux/io.h index 9595151d800d..469d53444218 100644 --- a/include/linux/io.h +++ b/include/linux/io.h @@ -166,4 +166,10 @@ static inline void arch_io_free_memtype_wc(resource_size_t base, } #endif +/* IO barriers */ + +#ifndef flush_wc_write +#define flush_wc_write() do { } while (0) +#endif + #endif /* _LINUX_IO_H */ -- 2.8.1