From mboxrd@z Thu Jan 1 00:00:00 1970 From: Miroslav Lichvar Subject: Improving accuracy of PHC readings Date: Fri, 19 Oct 2018 11:51:37 +0200 Message-ID: <20181019095137.GG4407@localhost> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: Richard Cochran , "Keller, Jacob E" To: netdev@vger.kernel.org Return-path: Received: from mx1.redhat.com ([209.132.183.28]:45094 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726690AbeJSR5S (ORCPT ); Fri, 19 Oct 2018 13:57:18 -0400 Content-Disposition: inline Sender: netdev-owner@vger.kernel.org List-ID: I think there might be a way how we could significantly improve accuracy of synchronization between the system clock and a PTP hardware clock, at least with some network drivers. Currently, the PTP_SYS_OFFSET ioctl reads the system clock, reads the PHC using the gettime64 function of the driver, and reads the system clock again. The ioctl can repeat this to provide multiple readings to the user space. phc2sys (or another program synchronizing the system clock to the PHC) assumes the PHC timestamps were captured in the middle between the two closest system clock timestamps. The trouble is that gettime64 typically reads multiple (2-3) registers and the timestamp is latched on the first one, so the assumption about middle point is wrong. There is an asymmetry, even if the delays on the PCIe bus are perfectly symmetric. A solution to this would be a new driver function that wraps the latching register read with readings of the system clock and return three timestamps instead of one. For example: ktime_get_real_ts64(&sys_ts1); IXGBE_READ_REG(hw, IXGBE_SYSTIMR); ktime_get_real_ts64(&sys_ts2); phc_ts.tv_nsec = IXGBE_READ_REG(hw, IXGBE_SYSTIML); phc_ts.tv_sec = IXGBE_READ_REG(hw, IXGBE_SYSTIMH); The extra timestamp doesn't fit the API of the PTP_SYS_OFFSET ioctl, so it would need to shift the timestamp it returns by the missing intervals (assuming the frequency offset between the PHC and system clock is small), or a new ioctl could be introduced that would return all timestamps in an array looking like this: [sys, phc, sys, sys, phc, sys, ...] This should significantly improve the accuracy of the synchronization, reduce the uncertainty in the readings to less than a half or third, and also reduce the jitter as there are fewer register reads sensitive to the PCIe delay. What do you think? -- Miroslav Lichvar