From mboxrd@z Thu Jan 1 00:00:00 1970 From: masahisa.kojima@linaro.org Subject: [PATCH net v2 2/3] net: socionext: Add dummy PHY register read in phy_write() Date: Tue, 23 Oct 2018 20:24:27 +0900 Message-ID: <20181023112428.6785-3-masahisa.kojima@linaro.org> References: <20181023112428.6785-1-masahisa.kojima@linaro.org> Cc: ilias.apalodimas@linaro.org, jaswinder.singh@linaro.org, ard.biesheuvel@linaro.org, osaki.yoshitoyo@socionext.com, Masahisa Kojima To: netdev@vger.kernel.org Return-path: Received: from mail-yw1-f67.google.com ([209.85.161.67]:35499 "EHLO mail-yw1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727873AbeJWTtf (ORCPT ); Tue, 23 Oct 2018 15:49:35 -0400 Received: by mail-yw1-f67.google.com with SMTP id y76-v6so379551ywd.2 for ; Tue, 23 Oct 2018 04:26:32 -0700 (PDT) In-Reply-To: <20181023112428.6785-1-masahisa.kojima@linaro.org> Sender: netdev-owner@vger.kernel.org List-ID: From: Masahisa Kojima There is a compatibility issue between RTL8211E implemented in Developerbox and netsec ethernet controller IP. Our MDIO controller stops MDC clock right after the write access, but RTL8211E expects MDC clock must be kept toggling for several clock cycle with MDIO high before entering the IDLE state. Without keeping clock after write access, write access is not correctly handled and register is not updated. To meet this requirement, netsec driver needs to issue dummy read(e.g. read PHYID1(offset 0x2) register) right after write access, to keep MDC clock. We think this compatibility issue is a problem specific to our MDIO controller and RTL8211E. Fixes: 533dd11a12f6 ("net: socionext: Add Synquacer NetSec driver") Signed-off-by: Masahisa Kojima Signed-off-by: Yoshitoyo Osaki --- changes in v2: - use the MACROs defiend in include/uapi/linux/mii.h drivers/net/ethernet/socionext/netsec.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/socionext/netsec.c b/drivers/net/ethernet/socionext/netsec.c index 829ed2718b22..5c295cc0b8f8 100644 --- a/drivers/net/ethernet/socionext/netsec.c +++ b/drivers/net/ethernet/socionext/netsec.c @@ -432,9 +432,12 @@ static int netsec_mac_update_to_phy_state(struct netsec_priv *priv) return 0; } +static int netsec_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr); + static int netsec_phy_write(struct mii_bus *bus, int phy_addr, int reg, u16 val) { + int status; struct netsec_priv *priv = bus->priv; if (netsec_mac_write(priv, GMAC_REG_GDR, val)) @@ -447,8 +450,19 @@ static int netsec_phy_write(struct mii_bus *bus, GMAC_REG_SHIFT_CR_GAR))) return -ETIMEDOUT; - return netsec_mac_wait_while_busy(priv, GMAC_REG_GAR, - NETSEC_GMAC_GAR_REG_GB); + status = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR, + NETSEC_GMAC_GAR_REG_GB); + + /* Developerbox implements RTL8211E PHY and there is + * a compatibility problem with F_GMAC4. + * RTL8211E expects MDC clock must be kept toggling for several + * clock cycle with MDIO high before entering the IDLE state. + * To meet this requirement, netsec driver needs to issue dummy + * read(e.g. read PHYID1(offset 0x2) register) right after write. + */ + netsec_phy_read(bus, phy_addr, MII_PHYSID1); + + return status; } static int netsec_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr) -- 2.14.2