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received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: bgPpes38+dJE2E/tO5dGswgOjVFD0rf6cblU1AGHG5VgnWH13rsfNEkXm0ocQoxfYQaqD0wHCPYQPddcOaf0RRgflpwESwhUT1FGlQRWn5Q96xBpfS3bHyeFgyE5EZGyJrhVbbf5elXJOkgFbeZWNfBY/BX2KR81R2/xEUj2VEx95m+MCkjdmD3Oda+Pop4LeaHtxwOHayRKGWhwa7RIHDG9eTozp9ISM6xF6K5OQQQuN+TPBNnpQTNe1OJMxGHg6NnMtiq/tmvq/vRonxOzFsAOqBWjdYJ0M5tAST3QMUCtUYZu/0v3Z2NL2PoKYSSq1qoU946G2lV3ngeWWYSWV54tRwK9EPHN5fZq8jygQic+IsP613tKL6CooJfI7TgF3SQwm1dFI4e5e9GnuA4sd7FOxlSL0JNOSjlNLIlsHbU= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7ec9cd55-3148-4590-c530-08d698cd94a6 X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Feb 2019 13:56:44.2654 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR05MB4358 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Shalom Toledo Add Spectrum-2 ASIC port type-speed operations. Since multiple ethtool link modes are represented using a single bit in the ASIC, the driver forces the user to configure all types per a specific speed. For example, if the user wants to advertise 100Gbps 4-lanes speed, he should advertise all the types of 100Gbps 4-lanes speed that are supported by the ASIC as shown below: Supported ethtool bits for 100Gbps 4-lanes: 0x1000000000 100000baseKR4 Full 0x2000000000 100000baseSR4 Full 0x4000000000 100000baseCR4 Full 0x8000000000 100000baseLR4_ER4 Full Command for advertising 100Gbps 4-lanes: ethtool -s enp3s0np1 advertise 0xF000000000 Signed-off-by: Shalom Toledo Acked-by: Jiri Pirko Signed-off-by: Ido Schimmel --- .../net/ethernet/mellanox/mlxsw/spectrum.c | 330 +++++++++++++++++- .../net/ethernet/mellanox/mlxsw/spectrum.h | 1 + 2 files changed, 330 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum.c b/drivers/net/e= thernet/mellanox/mlxsw/spectrum.c index fc0e7924233e..c55b478e48e9 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum.c @@ -2607,6 +2607,334 @@ mlxsw_sp1_port_type_speed_ops =3D { .reg_ptys_eth_unpack =3D mlxsw_sp1_reg_ptys_eth_unpack, }; =20 +static const enum ethtool_link_mode_bit_indices +mlxsw_sp2_mask_ethtool_sgmii_100m[] =3D { + ETHTOOL_LINK_MODE_100baseT_Full_BIT, +}; + +#define MLXSW_SP2_MASK_ETHTOOL_SGMII_100M_LEN \ + ARRAY_SIZE(mlxsw_sp2_mask_ethtool_sgmii_100m) + +static const enum ethtool_link_mode_bit_indices +mlxsw_sp2_mask_ethtool_1000base_x_sgmii[] =3D { + ETHTOOL_LINK_MODE_1000baseT_Full_BIT, + ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, +}; + +#define MLXSW_SP2_MASK_ETHTOOL_1000BASE_X_SGMII_LEN \ + ARRAY_SIZE(mlxsw_sp2_mask_ethtool_1000base_x_sgmii) + +static const enum ethtool_link_mode_bit_indices +mlxsw_sp2_mask_ethtool_2_5gbase_x_2_5gmii[] =3D { + ETHTOOL_LINK_MODE_2500baseX_Full_BIT, +}; + +#define MLXSW_SP2_MASK_ETHTOOL_2_5GBASE_X_2_5GMII_LEN \ + ARRAY_SIZE(mlxsw_sp2_mask_ethtool_2_5gbase_x_2_5gmii) + +static const enum ethtool_link_mode_bit_indices +mlxsw_sp2_mask_ethtool_5gbase_r[] =3D { + ETHTOOL_LINK_MODE_5000baseT_Full_BIT, +}; + +#define MLXSW_SP2_MASK_ETHTOOL_5GBASE_R_LEN \ + ARRAY_SIZE(mlxsw_sp2_mask_ethtool_5gbase_r) + +static const enum ethtool_link_mode_bit_indices +mlxsw_sp2_mask_ethtool_xfi_xaui_1_10g[] =3D { + ETHTOOL_LINK_MODE_10000baseT_Full_BIT, + ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, + ETHTOOL_LINK_MODE_10000baseR_FEC_BIT, + ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, + ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, + ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, + ETHTOOL_LINK_MODE_10000baseER_Full_BIT, +}; + +#define MLXSW_SP2_MASK_ETHTOOL_XFI_XAUI_1_10G_LEN \ + ARRAY_SIZE(mlxsw_sp2_mask_ethtool_xfi_xaui_1_10g) + +static const enum ethtool_link_mode_bit_indices +mlxsw_sp2_mask_ethtool_xlaui_4_xlppi_4_40g[] =3D { + ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, + ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, + ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, + ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, +}; + +#define MLXSW_SP2_MASK_ETHTOOL_XLAUI_4_XLPPI_4_40G_LEN \ + ARRAY_SIZE(mlxsw_sp2_mask_ethtool_xlaui_4_xlppi_4_40g) + +static const enum ethtool_link_mode_bit_indices +mlxsw_sp2_mask_ethtool_25gaui_1_25gbase_cr_kr[] =3D { + ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, + ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, + ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, +}; + +#define MLXSW_SP2_MASK_ETHTOOL_25GAUI_1_25GBASE_CR_KR_LEN \ + ARRAY_SIZE(mlxsw_sp2_mask_ethtool_25gaui_1_25gbase_cr_kr) + +static const enum ethtool_link_mode_bit_indices +mlxsw_sp2_mask_ethtool_50gaui_2_laui_2_50gbase_cr2_kr2[] =3D { + ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, + ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, + ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, +}; + +#define MLXSW_SP2_MASK_ETHTOOL_50GAUI_2_LAUI_2_50GBASE_CR2_KR2_LEN \ + ARRAY_SIZE(mlxsw_sp2_mask_ethtool_50gaui_2_laui_2_50gbase_cr2_kr2) + +static const enum ethtool_link_mode_bit_indices +mlxsw_sp2_mask_ethtool_caui_4_100gbase_cr4_kr4[] =3D { + ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, + ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, + ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, + ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, +}; + +#define MLXSW_SP2_MASK_ETHTOOL_CAUI_4_100GBASE_CR4_KR4_LEN \ + ARRAY_SIZE(mlxsw_sp2_mask_ethtool_caui_4_100gbase_cr4_kr4) + +struct mlxsw_sp2_port_link_mode { + const enum ethtool_link_mode_bit_indices *mask_ethtool; + int m_ethtool_len; + u32 mask; + u32 speed; +}; + +static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = =3D { + { + .mask =3D MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M, + .mask_ethtool =3D mlxsw_sp2_mask_ethtool_sgmii_100m, + .m_ethtool_len =3D MLXSW_SP2_MASK_ETHTOOL_SGMII_100M_LEN, + .speed =3D SPEED_100, + }, + { + .mask =3D MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII, + .mask_ethtool =3D mlxsw_sp2_mask_ethtool_1000base_x_sgmii, + .m_ethtool_len =3D MLXSW_SP2_MASK_ETHTOOL_1000BASE_X_SGMII_LEN, + .speed =3D SPEED_1000, + }, + { + .mask =3D MLXSW_REG_PTYS_EXT_ETH_SPEED_2_5GBASE_X_2_5GMII, + .mask_ethtool =3D mlxsw_sp2_mask_ethtool_2_5gbase_x_2_5gmii, + .m_ethtool_len =3D MLXSW_SP2_MASK_ETHTOOL_2_5GBASE_X_2_5GMII_LEN, + .speed =3D SPEED_2500, + }, + { + .mask =3D MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R, + .mask_ethtool =3D mlxsw_sp2_mask_ethtool_5gbase_r, + .m_ethtool_len =3D MLXSW_SP2_MASK_ETHTOOL_5GBASE_R_LEN, + .speed =3D SPEED_5000, + }, + { + .mask =3D MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G, + .mask_ethtool =3D mlxsw_sp2_mask_ethtool_xfi_xaui_1_10g, + .m_ethtool_len =3D MLXSW_SP2_MASK_ETHTOOL_XFI_XAUI_1_10G_LEN, + .speed =3D SPEED_10000, + }, + { + .mask =3D MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G, + .mask_ethtool =3D mlxsw_sp2_mask_ethtool_xlaui_4_xlppi_4_40g, + .m_ethtool_len =3D MLXSW_SP2_MASK_ETHTOOL_XLAUI_4_XLPPI_4_40G_LEN, + .speed =3D SPEED_40000, + }, + { + .mask =3D MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR, + .mask_ethtool =3D mlxsw_sp2_mask_ethtool_25gaui_1_25gbase_cr_kr, + .m_ethtool_len =3D MLXSW_SP2_MASK_ETHTOOL_25GAUI_1_25GBASE_CR_KR_LEN, + .speed =3D SPEED_25000, + }, + { + .mask =3D MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2, + .mask_ethtool =3D mlxsw_sp2_mask_ethtool_50gaui_2_laui_2_50gbase_cr2_kr2= , + .m_ethtool_len =3D MLXSW_SP2_MASK_ETHTOOL_50GAUI_2_LAUI_2_50GBASE_CR2_KR= 2_LEN, + .speed =3D SPEED_50000, + }, + { + .mask =3D MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4, + .mask_ethtool =3D mlxsw_sp2_mask_ethtool_caui_4_100gbase_cr4_kr4, + .m_ethtool_len =3D MLXSW_SP2_MASK_ETHTOOL_CAUI_4_100GBASE_CR4_KR4_LEN, + .speed =3D SPEED_100000, + }, +}; + +#define MLXSW_SP2_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp2_port_link_mode) + +static void +mlxsw_sp2_from_ptys_supported_port(struct mlxsw_sp *mlxsw_sp, + u32 ptys_eth_proto, + struct ethtool_link_ksettings *cmd) +{ + ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE); + ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane); +} + +static void +mlxsw_sp2_set_bit_ethtool(const struct mlxsw_sp2_port_link_mode *link_mode= , + unsigned long *mode) +{ + int i; + + for (i =3D 0; i < link_mode->m_ethtool_len; i++) + __set_bit(link_mode->mask_ethtool[i], mode); +} + +static void +mlxsw_sp2_from_ptys_link(struct mlxsw_sp *mlxsw_sp, u32 ptys_eth_proto, + unsigned long *mode) +{ + int i; + + for (i =3D 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) { + if (ptys_eth_proto & mlxsw_sp2_port_link_mode[i].mask) + mlxsw_sp2_set_bit_ethtool(&mlxsw_sp2_port_link_mode[i], + mode); + } +} + +static void +mlxsw_sp2_from_ptys_speed_duplex(struct mlxsw_sp *mlxsw_sp, bool carrier_o= k, + u32 ptys_eth_proto, + struct ethtool_link_ksettings *cmd) +{ + u32 speed =3D SPEED_UNKNOWN; + u8 duplex =3D DUPLEX_UNKNOWN; + int i; + + if (!carrier_ok) + goto out; + + for (i =3D 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) { + if (ptys_eth_proto & mlxsw_sp2_port_link_mode[i].mask) { + speed =3D mlxsw_sp2_port_link_mode[i].speed; + duplex =3D DUPLEX_FULL; + break; + } + } +out: + cmd->base.speed =3D speed; + cmd->base.duplex =3D duplex; +} + +static bool +mlxsw_sp2_test_bit_ethtool(const struct mlxsw_sp2_port_link_mode *link_mod= e, + const unsigned long *mode) +{ + int cnt =3D 0; + int i; + + for (i =3D 0; i < link_mode->m_ethtool_len; i++) { + if (test_bit(link_mode->mask_ethtool[i], mode)) + cnt++; + } + + return cnt =3D=3D link_mode->m_ethtool_len; +} + +static u32 +mlxsw_sp2_to_ptys_advert_link(struct mlxsw_sp *mlxsw_sp, + const struct ethtool_link_ksettings *cmd) +{ + u32 ptys_proto =3D 0; + int i; + + for (i =3D 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) { + if (mlxsw_sp2_test_bit_ethtool(&mlxsw_sp2_port_link_mode[i], + cmd->link_modes.advertising)) + ptys_proto |=3D mlxsw_sp2_port_link_mode[i].mask; + } + return ptys_proto; +} + +static u32 mlxsw_sp2_to_ptys_speed(struct mlxsw_sp *mlxsw_sp, u32 speed) +{ + u32 ptys_proto =3D 0; + int i; + + for (i =3D 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) { + if (speed =3D=3D mlxsw_sp2_port_link_mode[i].speed) + ptys_proto |=3D mlxsw_sp2_port_link_mode[i].mask; + } + return ptys_proto; +} + +static u32 +mlxsw_sp2_to_ptys_upper_speed(struct mlxsw_sp *mlxsw_sp, u32 upper_speed) +{ + u32 ptys_proto =3D 0; + int i; + + for (i =3D 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) { + if (mlxsw_sp2_port_link_mode[i].speed <=3D upper_speed) + ptys_proto |=3D mlxsw_sp2_port_link_mode[i].mask; + } + return ptys_proto; +} + +static int +mlxsw_sp2_port_speed_base(struct mlxsw_sp *mlxsw_sp, u8 local_port, + u32 *base_speed) +{ + char ptys_pl[MLXSW_REG_PTYS_LEN]; + u32 eth_proto_cap; + int err; + + /* In Spectrum-2, the speed of 1x can change from port to port, so query + * it from firmware. + */ + mlxsw_reg_ptys_ext_eth_pack(ptys_pl, local_port, 0, false); + err =3D mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); + if (err) + return err; + mlxsw_reg_ptys_ext_eth_unpack(ptys_pl, ð_proto_cap, NULL, NULL); + + if (eth_proto_cap & + MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR) { + *base_speed =3D MLXSW_SP_PORT_BASE_SPEED_50G; + return 0; + } + + if (eth_proto_cap & + MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR) { + *base_speed =3D MLXSW_SP_PORT_BASE_SPEED_25G; + return 0; + } + + return -EIO; +} + +static void +mlxsw_sp2_reg_ptys_eth_pack(struct mlxsw_sp *mlxsw_sp, char *payload, + u8 local_port, u32 proto_admin, + bool autoneg) +{ + mlxsw_reg_ptys_ext_eth_pack(payload, local_port, proto_admin, autoneg); +} + +static void +mlxsw_sp2_reg_ptys_eth_unpack(struct mlxsw_sp *mlxsw_sp, char *payload, + u32 *p_eth_proto_cap, u32 *p_eth_proto_admin, + u32 *p_eth_proto_oper) +{ + mlxsw_reg_ptys_ext_eth_unpack(payload, p_eth_proto_cap, + p_eth_proto_admin, p_eth_proto_oper); +} + +static const struct mlxsw_sp_port_type_speed_ops +mlxsw_sp2_port_type_speed_ops =3D { + .from_ptys_supported_port =3D mlxsw_sp2_from_ptys_supported_port, + .from_ptys_link =3D mlxsw_sp2_from_ptys_link, + .from_ptys_speed_duplex =3D mlxsw_sp2_from_ptys_speed_duplex, + .to_ptys_advert_link =3D mlxsw_sp2_to_ptys_advert_link, + .to_ptys_speed =3D mlxsw_sp2_to_ptys_speed, + .to_ptys_upper_speed =3D mlxsw_sp2_to_ptys_upper_speed, + .port_speed_base =3D mlxsw_sp2_port_speed_base, + .reg_ptys_eth_pack =3D mlxsw_sp2_reg_ptys_eth_pack, + .reg_ptys_eth_unpack =3D mlxsw_sp2_reg_ptys_eth_unpack, +}; + static void mlxsw_sp_port_get_link_supported(struct mlxsw_sp *mlxsw_sp, u32 eth_proto_= cap, struct ethtool_link_ksettings *cmd) @@ -4189,7 +4517,7 @@ static int mlxsw_sp2_init(struct mlxsw_core *mlxsw_co= re, mlxsw_sp->mac_mask =3D mlxsw_sp2_mac_mask; mlxsw_sp->rif_ops_arr =3D mlxsw_sp2_rif_ops_arr; mlxsw_sp->sb_vals =3D &mlxsw_sp2_sb_vals; - mlxsw_sp->port_type_speed_ops =3D &mlxsw_sp1_port_type_speed_ops; + mlxsw_sp->port_type_speed_ops =3D &mlxsw_sp2_port_type_speed_ops; =20 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info); } diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum.h b/drivers/net/e= thernet/mellanox/mlxsw/spectrum.h index d4f53632b24c..a61c1130d9e3 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum.h +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum.h @@ -34,6 +34,7 @@ #define MLXSW_SP_PORTS_PER_CLUSTER_MAX 4 =20 #define MLXSW_SP_PORT_BASE_SPEED_25G 25000 /* Mb/s */ +#define MLXSW_SP_PORT_BASE_SPEED_50G 50000 /* Mb/s */ =20 #define MLXSW_SP_KVD_LINEAR_SIZE 98304 /* entries */ #define MLXSW_SP_KVD_GRANULARITY 128 --=20 2.20.1