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Date:   Tue, 4 Jun 2019 23:58:54 +0200
From:   Andrew Lunn <andrew@lunn.ch>
To:     Robert Hancock <hancock@sedsystems.ca>
Cc:     netdev@vger.kernel.org, anirudh@xilinx.com, John.Linn@xilinx.com
Subject: Re: [PATCH net-next v3 00/19] Xilinx axienet driver updates (v3)
Message-ID: <20190604215854.GY19627@lunn.ch>
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On Tue, Jun 04, 2019 at 03:43:27PM -0600, Robert Hancock wrote:
> This is a series of enhancements and bug fixes in order to get the mainline
> version of this driver into a more generally usable state, including on
> x86 or ARM platforms. It also converts the driver to use the phylink API
> in order to provide support for SFP modules.
> 
> Changes since v2:
> -Fixed MDIO bus parent detection as suggested by Andrew Lunn
> -Use clock framework to detect AXI bus clock rather than having to explicitly
>  specify MDIO clock divisor
> -Hold MDIO bus lock around device resets to avoid concurrent MDIO accesses
> -Fix bug in "Make missing MAC address non-fatal" patch

Hi Robert

When you repost, please include all reviewed-by, acked-by tags etc.

     Andrew