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* [PATCH net-next 00/10] net: stmmac: 10GbE using XGMAC
@ 2019-06-26 13:47 Jose Abreu
  2019-06-26 13:47 ` [PATCH net-next 01/10] net: stmmac: dwxgmac: Enable EDMA by default Jose Abreu
                   ` (9 more replies)
  0 siblings, 10 replies; 20+ messages in thread
From: Jose Abreu @ 2019-06-26 13:47 UTC (permalink / raw)
  To: linux-kernel, netdev
  Cc: Jose Abreu, Joao Pinto, David S . Miller, Giuseppe Cavallaro,
	Alexandre Torgue

Support for 10Gb Link using XGMAC core plus some performance tweaks.

Tested in a PCI based setup.

iperf3 TCP results:
	TSO ON, MTU=1500, TX Queues = 1, RX Queues = 1, Flow Control ON
	Pinned CPU (-A), Zero-Copy (-Z)

[ ID] Interval           Transfer     Bitrate         Retr
[  5]   0.00-600.00 sec   643 GBytes  9.21 Gbits/sec    1             sender
[  5]   0.00-600.00 sec   643 GBytes  9.21 Gbits/sec                  receiver

Cc: Joao Pinto <jpinto@synopsys.com>
Cc: David S. Miller <davem@davemloft.net>
Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Cc: Alexandre Torgue <alexandre.torgue@st.com>

Jose Abreu (10):
  net: stmmac: dwxgmac: Enable EDMA by default
  net: stmmac: Do not try to enable PHY EEE if MAC does not support it
  net: stmmac: Decrease default RX Watchdog value
  net: stmmac: dwxgmac: Fix the undefined burst setting
  net: stmmac: Add the missing speeds that XGMAC supports
  net: stmmac: Do not disable interrupts when cleaning TX
  net: stmmac: Enable support for > 32 Bits addressing in XGMAC
  net: stmmac: Update RX Tail Pointer to last free entry
  net: stmmac: Only disable interrupts if NAPI is scheduled
  net: stmmac: Try to get C45 PHY if everything else fails

 drivers/net/ethernet/stmicro/stmmac/common.h       |   9 +-
 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h     |  14 +-
 .../net/ethernet/stmicro/stmmac/dwxgmac2_core.c    |  14 +-
 .../net/ethernet/stmicro/stmmac/dwxgmac2_descs.c   |   4 +-
 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c |  27 +++-
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c  | 165 ++++++++++++++++-----
 6 files changed, 178 insertions(+), 55 deletions(-)

-- 
2.7.4


^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH net-next 01/10] net: stmmac: dwxgmac: Enable EDMA by default
  2019-06-26 13:47 [PATCH net-next 00/10] net: stmmac: 10GbE using XGMAC Jose Abreu
@ 2019-06-26 13:47 ` Jose Abreu
  2019-06-26 16:33   ` David Miller
  2019-06-26 13:47 ` [PATCH net-next 02/10] net: stmmac: Do not try to enable PHY EEE if MAC does not support it Jose Abreu
                   ` (8 subsequent siblings)
  9 siblings, 1 reply; 20+ messages in thread
From: Jose Abreu @ 2019-06-26 13:47 UTC (permalink / raw)
  To: linux-kernel, netdev
  Cc: Jose Abreu, Joao Pinto, David S . Miller, Giuseppe Cavallaro,
	Alexandre Torgue

Enable the EDMA feature by default which gives higher performance.

Signed-off-by: Jose Abreu <joabreu@synopsys.com>
Cc: Joao Pinto <jpinto@synopsys.com>
Cc: David S. Miller <davem@davemloft.net>
Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
---
 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h     | 2 ++
 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
index b8296eb41011..50b41ecb0325 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
@@ -177,6 +177,8 @@
 #define XGMAC_BLEN8			BIT(2)
 #define XGMAC_BLEN4			BIT(1)
 #define XGMAC_UNDEF			BIT(0)
+#define XGMAC_TX_EDMA_CTRL		0x00003040
+#define XGMAC_RX_EDMA_CTRL		0x00003044
 #define XGMAC_DMA_CH_CONTROL(x)		(0x00003100 + (0x80 * (x)))
 #define XGMAC_PBLx8			BIT(16)
 #define XGMAC_DMA_CH_TX_CONTROL(x)	(0x00003104 + (0x80 * (x)))
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
index 7861a938420a..a1ad49680c07 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
@@ -122,6 +122,8 @@ static void dwxgmac2_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
 	}
 
 	writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
+	writel(GENMASK(29, 0), ioaddr + XGMAC_TX_EDMA_CTRL);
+	writel(GENMASK(29, 0), ioaddr + XGMAC_RX_EDMA_CTRL);
 }
 
 static void dwxgmac2_dma_rx_mode(void __iomem *ioaddr, int mode,
-- 
2.7.4


^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH net-next 02/10] net: stmmac: Do not try to enable PHY EEE if MAC does not support it
  2019-06-26 13:47 [PATCH net-next 00/10] net: stmmac: 10GbE using XGMAC Jose Abreu
  2019-06-26 13:47 ` [PATCH net-next 01/10] net: stmmac: dwxgmac: Enable EDMA by default Jose Abreu
@ 2019-06-26 13:47 ` Jose Abreu
  2019-06-26 13:47 ` [PATCH net-next 03/10] net: stmmac: Decrease default RX Watchdog value Jose Abreu
                   ` (7 subsequent siblings)
  9 siblings, 0 replies; 20+ messages in thread
From: Jose Abreu @ 2019-06-26 13:47 UTC (permalink / raw)
  To: linux-kernel, netdev
  Cc: Jose Abreu, Joao Pinto, David S . Miller, Giuseppe Cavallaro,
	Alexandre Torgue

Do not enable EEE feature in the PHY if MAC does not support it.

Signed-off-by: Jose Abreu <joabreu@synopsys.com>
Cc: Joao Pinto <jpinto@synopsys.com>
Cc: David S. Miller <davem@davemloft.net>
Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
---
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index f4593d2d9d20..fab65f129207 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -893,7 +893,7 @@ static void stmmac_mac_link_up(struct phylink_config *config,
 	struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 
 	stmmac_mac_set(priv, priv->ioaddr, true);
-	if (phy) {
+	if (phy && priv->dma_cap.eee) {
 		priv->eee_active = phy_init_eee(phy, 1) >= 0;
 		priv->eee_enabled = stmmac_eee_init(priv);
 		stmmac_set_eee_pls(priv, priv->hw, true);
-- 
2.7.4


^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH net-next 03/10] net: stmmac: Decrease default RX Watchdog value
  2019-06-26 13:47 [PATCH net-next 00/10] net: stmmac: 10GbE using XGMAC Jose Abreu
  2019-06-26 13:47 ` [PATCH net-next 01/10] net: stmmac: dwxgmac: Enable EDMA by default Jose Abreu
  2019-06-26 13:47 ` [PATCH net-next 02/10] net: stmmac: Do not try to enable PHY EEE if MAC does not support it Jose Abreu
@ 2019-06-26 13:47 ` Jose Abreu
  2019-06-26 13:47 ` [PATCH net-next 04/10] net: stmmac: dwxgmac: Fix the undefined burst setting Jose Abreu
                   ` (6 subsequent siblings)
  9 siblings, 0 replies; 20+ messages in thread
From: Jose Abreu @ 2019-06-26 13:47 UTC (permalink / raw)
  To: linux-kernel, netdev
  Cc: Jose Abreu, Joao Pinto, David S . Miller, Giuseppe Cavallaro,
	Alexandre Torgue

For performance reasons decrease the default RX Watchdog value for the
minimum allowed.

Signed-off-by: Jose Abreu <joabreu@synopsys.com>
Cc: Joao Pinto <jpinto@synopsys.com>
Cc: David S. Miller <davem@davemloft.net>
Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
---
 drivers/net/ethernet/stmicro/stmmac/common.h      | 2 +-
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h
index ad9e9368535d..14d8f6d7cb9a 100644
--- a/drivers/net/ethernet/stmicro/stmmac/common.h
+++ b/drivers/net/ethernet/stmicro/stmmac/common.h
@@ -246,7 +246,7 @@ struct stmmac_safety_stats {
 
 /* Max/Min RI Watchdog Timer count value */
 #define MAX_DMA_RIWT		0xff
-#define MIN_DMA_RIWT		0x20
+#define MIN_DMA_RIWT		0x10
 /* Tx coalesce parameters */
 #define STMMAC_COAL_TX_TIMER	1000
 #define STMMAC_MAX_COAL_TX_TICK	100000
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index fab65f129207..dc57a2c0a630 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -2512,9 +2512,9 @@ static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
 	priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
 
 	if (priv->use_riwt) {
-		ret = stmmac_rx_watchdog(priv, priv->ioaddr, MAX_DMA_RIWT, rx_cnt);
+		ret = stmmac_rx_watchdog(priv, priv->ioaddr, MIN_DMA_RIWT, rx_cnt);
 		if (!ret)
-			priv->rx_riwt = MAX_DMA_RIWT;
+			priv->rx_riwt = MIN_DMA_RIWT;
 	}
 
 	if (priv->hw->pcs)
-- 
2.7.4


^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH net-next 04/10] net: stmmac: dwxgmac: Fix the undefined burst setting
  2019-06-26 13:47 [PATCH net-next 00/10] net: stmmac: 10GbE using XGMAC Jose Abreu
                   ` (2 preceding siblings ...)
  2019-06-26 13:47 ` [PATCH net-next 03/10] net: stmmac: Decrease default RX Watchdog value Jose Abreu
@ 2019-06-26 13:47 ` Jose Abreu
  2019-06-26 13:47 ` [PATCH net-next 05/10] net: stmmac: Add the missing speeds that XGMAC supports Jose Abreu
                   ` (5 subsequent siblings)
  9 siblings, 0 replies; 20+ messages in thread
From: Jose Abreu @ 2019-06-26 13:47 UTC (permalink / raw)
  To: linux-kernel, netdev
  Cc: Jose Abreu, Joao Pinto, David S . Miller, Giuseppe Cavallaro,
	Alexandre Torgue

Undefined burst shall only be set if pdata asks to.

Signed-off-by: Jose Abreu <joabreu@synopsys.com>
Cc: Joao Pinto <jpinto@synopsys.com>
Cc: David S. Miller <davem@davemloft.net>
Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
---
 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
index a1ad49680c07..3f84271da836 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
@@ -91,11 +91,11 @@ static void dwxgmac2_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
 	value |= (axi->axi_rd_osr_lmt << XGMAC_RD_OSR_LMT_SHIFT) &
 		XGMAC_RD_OSR_LMT;
 
+	if (!axi->axi_fb)
+		value |= XGMAC_UNDEF;
+
 	value &= ~XGMAC_BLEN;
 	for (i = 0; i < AXI_BLEN; i++) {
-		if (axi->axi_blen[i])
-			value &= ~XGMAC_UNDEF;
-
 		switch (axi->axi_blen[i]) {
 		case 256:
 			value |= XGMAC_BLEN256;
-- 
2.7.4


^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH net-next 05/10] net: stmmac: Add the missing speeds that XGMAC supports
  2019-06-26 13:47 [PATCH net-next 00/10] net: stmmac: 10GbE using XGMAC Jose Abreu
                   ` (3 preceding siblings ...)
  2019-06-26 13:47 ` [PATCH net-next 04/10] net: stmmac: dwxgmac: Fix the undefined burst setting Jose Abreu
@ 2019-06-26 13:47 ` Jose Abreu
  2019-06-26 13:47 ` [PATCH net-next 06/10] net: stmmac: Do not disable interrupts when cleaning TX Jose Abreu
                   ` (4 subsequent siblings)
  9 siblings, 0 replies; 20+ messages in thread
From: Jose Abreu @ 2019-06-26 13:47 UTC (permalink / raw)
  To: linux-kernel, netdev
  Cc: Jose Abreu, Joao Pinto, David S . Miller, Giuseppe Cavallaro,
	Alexandre Torgue

XGMAC supports following speeds:
	- 10G XGMII
	- 5G XGMII
	- 2.5G XGMII
	- 2.5G GMII
	- 1G GMII
	- 100M MII
	- 10M MII

Add them to the stmmac driver.

Signed-off-by: Jose Abreu <joabreu@synopsys.com>
Cc: Joao Pinto <jpinto@synopsys.com>
Cc: David S. Miller <davem@davemloft.net>
Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
---
 drivers/net/ethernet/stmicro/stmmac/common.h       |  6 +-
 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h     | 10 ++-
 .../net/ethernet/stmicro/stmmac/dwxgmac2_core.c    | 14 ++--
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c  | 79 ++++++++++++++++++----
 4 files changed, 86 insertions(+), 23 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h
index 14d8f6d7cb9a..9e8f4dbdcc22 100644
--- a/drivers/net/ethernet/stmicro/stmmac/common.h
+++ b/drivers/net/ethernet/stmicro/stmmac/common.h
@@ -392,8 +392,12 @@ struct mac_link {
 	u32 speed100;
 	u32 speed1000;
 	u32 speed2500;
-	u32 speed10000;
 	u32 duplex;
+	struct {
+		u32 speed2500;
+		u32 speed5000;
+		u32 speed10000;
+	} xgmii;
 };
 
 struct mii_regs {
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
index 50b41ecb0325..9077b54cbfac 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
@@ -15,10 +15,14 @@
 /* MAC Registers */
 #define XGMAC_TX_CONFIG			0x00000000
 #define XGMAC_CONFIG_SS_OFF		29
-#define XGMAC_CONFIG_SS_MASK		GENMASK(30, 29)
+#define XGMAC_CONFIG_SS_MASK		GENMASK(31, 29)
 #define XGMAC_CONFIG_SS_10000		(0x0 << XGMAC_CONFIG_SS_OFF)
-#define XGMAC_CONFIG_SS_2500		(0x2 << XGMAC_CONFIG_SS_OFF)
-#define XGMAC_CONFIG_SS_1000		(0x3 << XGMAC_CONFIG_SS_OFF)
+#define XGMAC_CONFIG_SS_2500_GMII	(0x2 << XGMAC_CONFIG_SS_OFF)
+#define XGMAC_CONFIG_SS_1000_GMII	(0x3 << XGMAC_CONFIG_SS_OFF)
+#define XGMAC_CONFIG_SS_100_MII		(0x4 << XGMAC_CONFIG_SS_OFF)
+#define XGMAC_CONFIG_SS_5000		(0x5 << XGMAC_CONFIG_SS_OFF)
+#define XGMAC_CONFIG_SS_2500		(0x6 << XGMAC_CONFIG_SS_OFF)
+#define XGMAC_CONFIG_SS_10_MII		(0x7 << XGMAC_CONFIG_SS_OFF)
 #define XGMAC_CONFIG_SARC		GENMASK(22, 20)
 #define XGMAC_CONFIG_SARC_SHIFT		20
 #define XGMAC_CONFIG_JD			BIT(16)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
index bfa7d6913fd4..0a32c96a7854 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
@@ -36,7 +36,7 @@ static void dwxgmac2_core_init(struct mac_device_info *hw,
 
 		switch (hw->ps) {
 		case SPEED_10000:
-			tx |= hw->link.speed10000;
+			tx |= hw->link.xgmii.speed10000;
 			break;
 		case SPEED_2500:
 			tx |= hw->link.speed2500;
@@ -381,11 +381,13 @@ int dwxgmac2_setup(struct stmmac_priv *priv)
 		mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
 
 	mac->link.duplex = 0;
-	mac->link.speed10 = 0;
-	mac->link.speed100 = 0;
-	mac->link.speed1000 = XGMAC_CONFIG_SS_1000;
-	mac->link.speed2500 = XGMAC_CONFIG_SS_2500;
-	mac->link.speed10000 = XGMAC_CONFIG_SS_10000;
+	mac->link.speed10 = XGMAC_CONFIG_SS_10_MII;
+	mac->link.speed100 = XGMAC_CONFIG_SS_100_MII;
+	mac->link.speed1000 = XGMAC_CONFIG_SS_1000_GMII;
+	mac->link.speed2500 = XGMAC_CONFIG_SS_2500_GMII;
+	mac->link.xgmii.speed2500 = XGMAC_CONFIG_SS_2500;
+	mac->link.xgmii.speed5000 = XGMAC_CONFIG_SS_5000;
+	mac->link.xgmii.speed10000 = XGMAC_CONFIG_SS_10000;
 	mac->link.speed_mask = XGMAC_CONFIG_SS_MASK;
 
 	mac->mii.addr = XGMAC_MDIO_ADDR;
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index dc57a2c0a630..1247066c371c 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -802,14 +802,43 @@ static void stmmac_validate(struct phylink_config *config,
 			    struct phylink_link_state *state)
 {
 	struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
+	__ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, };
 	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
 	int tx_cnt = priv->plat->tx_queues_to_use;
 	int max_speed = priv->plat->max_speed;
 
+	phylink_set(mac_supported, 10baseT_Half);
+	phylink_set(mac_supported, 10baseT_Full);
+	phylink_set(mac_supported, 100baseT_Half);
+	phylink_set(mac_supported, 100baseT_Full);
+
+	phylink_set(mac_supported, Autoneg);
+	phylink_set(mac_supported, Pause);
+	phylink_set(mac_supported, Asym_Pause);
+	phylink_set_port_modes(mac_supported);
+
+	if (priv->plat->has_gmac ||
+	    priv->plat->has_gmac4 ||
+	    priv->plat->has_xgmac) {
+		phylink_set(mac_supported, 1000baseT_Half);
+		phylink_set(mac_supported, 1000baseT_Full);
+		phylink_set(mac_supported, 1000baseKX_Full);
+	}
+
 	/* Cut down 1G if asked to */
 	if ((max_speed > 0) && (max_speed < 1000)) {
 		phylink_set(mask, 1000baseT_Full);
 		phylink_set(mask, 1000baseX_Full);
+	} else if (priv->plat->has_xgmac) {
+		phylink_set(mac_supported, 2500baseT_Full);
+		phylink_set(mac_supported, 5000baseT_Full);
+		phylink_set(mac_supported, 10000baseSR_Full);
+		phylink_set(mac_supported, 10000baseLR_Full);
+		phylink_set(mac_supported, 10000baseER_Full);
+		phylink_set(mac_supported, 10000baseLRM_Full);
+		phylink_set(mac_supported, 10000baseT_Full);
+		phylink_set(mac_supported, 10000baseKX4_Full);
+		phylink_set(mac_supported, 10000baseKR_Full);
 	}
 
 	/* Half-Duplex can only work with single queue */
@@ -819,7 +848,12 @@ static void stmmac_validate(struct phylink_config *config,
 		phylink_set(mask, 1000baseT_Half);
 	}
 
-	bitmap_andnot(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
+	bitmap_and(supported, supported, mac_supported,
+		   __ETHTOOL_LINK_MODE_MASK_NBITS);
+	bitmap_andnot(supported, supported, mask,
+		      __ETHTOOL_LINK_MODE_MASK_NBITS);
+	bitmap_and(state->advertising, state->advertising, mac_supported,
+		   __ETHTOOL_LINK_MODE_MASK_NBITS);
 	bitmap_andnot(state->advertising, state->advertising, mask,
 		      __ETHTOOL_LINK_MODE_MASK_NBITS);
 }
@@ -839,18 +873,37 @@ static void stmmac_mac_config(struct phylink_config *config, unsigned int mode,
 	ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
 	ctrl &= ~priv->hw->link.speed_mask;
 
-	switch (state->speed) {
-	case SPEED_1000:
-		ctrl |= priv->hw->link.speed1000;
-		break;
-	case SPEED_100:
-		ctrl |= priv->hw->link.speed100;
-		break;
-	case SPEED_10:
-		ctrl |= priv->hw->link.speed10;
-		break;
-	default:
-		return;
+	if (state->interface == PHY_INTERFACE_MODE_USXGMII) {
+		switch (state->speed) {
+		case SPEED_10000:
+			ctrl |= priv->hw->link.xgmii.speed10000;
+			break;
+		case SPEED_5000:
+			ctrl |= priv->hw->link.xgmii.speed5000;
+			break;
+		case SPEED_2500:
+			ctrl |= priv->hw->link.xgmii.speed2500;
+			break;
+		default:
+			return;
+		}
+	} else {
+		switch (state->speed) {
+		case SPEED_2500:
+			ctrl |= priv->hw->link.speed2500;
+			break;
+		case SPEED_1000:
+			ctrl |= priv->hw->link.speed1000;
+			break;
+		case SPEED_100:
+			ctrl |= priv->hw->link.speed100;
+			break;
+		case SPEED_10:
+			ctrl |= priv->hw->link.speed10;
+			break;
+		default:
+			return;
+		}
 	}
 
 	priv->speed = state->speed;
-- 
2.7.4


^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH net-next 06/10] net: stmmac: Do not disable interrupts when cleaning TX
  2019-06-26 13:47 [PATCH net-next 00/10] net: stmmac: 10GbE using XGMAC Jose Abreu
                   ` (4 preceding siblings ...)
  2019-06-26 13:47 ` [PATCH net-next 05/10] net: stmmac: Add the missing speeds that XGMAC supports Jose Abreu
@ 2019-06-26 13:47 ` Jose Abreu
  2019-06-26 13:47 ` [PATCH net-next 07/10] net: stmmac: Enable support for > 32 Bits addressing in XGMAC Jose Abreu
                   ` (3 subsequent siblings)
  9 siblings, 0 replies; 20+ messages in thread
From: Jose Abreu @ 2019-06-26 13:47 UTC (permalink / raw)
  To: linux-kernel, netdev
  Cc: Jose Abreu, Joao Pinto, David S . Miller, Giuseppe Cavallaro,
	Alexandre Torgue

This is a performance killer and anyways the interrupts are being
disabled by RX NAPI so no need to disable them again.

Signed-off-by: Jose Abreu <joabreu@synopsys.com>
Cc: Joao Pinto <jpinto@synopsys.com>
Cc: David S. Miller <davem@davemloft.net>
Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
---
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 1247066c371c..3a6fac22854e 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -2057,10 +2057,8 @@ static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan)
 		napi_schedule_irqoff(&ch->rx_napi);
 	}
 
-	if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) {
-		stmmac_disable_dma_irq(priv, priv->ioaddr, chan);
+	if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use))
 		napi_schedule_irqoff(&ch->tx_napi);
-	}
 
 	return status;
 }
@@ -3560,8 +3558,8 @@ static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget)
 	work_done = stmmac_tx_clean(priv, DMA_TX_SIZE, chan);
 	work_done = min(work_done, budget);
 
-	if (work_done < budget && napi_complete_done(napi, work_done))
-		stmmac_enable_dma_irq(priv, priv->ioaddr, chan);
+	if (work_done < budget)
+		napi_complete_done(napi, work_done);
 
 	/* Force transmission restart */
 	tx_q = &priv->tx_queue[chan];
-- 
2.7.4


^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH net-next 07/10] net: stmmac: Enable support for > 32 Bits addressing in XGMAC
  2019-06-26 13:47 [PATCH net-next 00/10] net: stmmac: 10GbE using XGMAC Jose Abreu
                   ` (5 preceding siblings ...)
  2019-06-26 13:47 ` [PATCH net-next 06/10] net: stmmac: Do not disable interrupts when cleaning TX Jose Abreu
@ 2019-06-26 13:47 ` Jose Abreu
  2019-06-26 20:19   ` Andrew Lunn
  2019-06-26 13:47 ` [PATCH net-next 08/10] net: stmmac: Update RX Tail Pointer to last free entry Jose Abreu
                   ` (2 subsequent siblings)
  9 siblings, 1 reply; 20+ messages in thread
From: Jose Abreu @ 2019-06-26 13:47 UTC (permalink / raw)
  To: linux-kernel, netdev
  Cc: Jose Abreu, Joao Pinto, David S . Miller, Giuseppe Cavallaro,
	Alexandre Torgue

Currently, stmmac only supports 32 bits addressing for SKB. Enable the
support for upto 48 bits addressing in XGMAC core.

This avoids the use of bounce buffers and increases performance.

Signed-off-by: Jose Abreu <joabreu@synopsys.com>
Cc: Joao Pinto <jpinto@synopsys.com>
Cc: David S. Miller <davem@davemloft.net>
Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
---
 drivers/net/ethernet/stmicro/stmmac/common.h       |  1 +
 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h     |  2 +
 .../net/ethernet/stmicro/stmmac/dwxgmac2_descs.c   |  4 +-
 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 19 ++++++++-
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c  | 46 ++++++++++++++++------
 5 files changed, 57 insertions(+), 15 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h
index 9e8f4dbdcc22..2403a65167b2 100644
--- a/drivers/net/ethernet/stmicro/stmmac/common.h
+++ b/drivers/net/ethernet/stmicro/stmmac/common.h
@@ -351,6 +351,7 @@ struct dma_features {
 	unsigned int frpsel;
 	unsigned int frpbs;
 	unsigned int frpes;
+	unsigned int addr64;
 };
 
 /* GMAC TX FIFO is 8K, Rx FIFO is 16K */
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
index 9077b54cbfac..49b0d945052c 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
@@ -87,6 +87,7 @@
 #define XGMAC_HWFEAT_GMIISEL		BIT(1)
 #define XGMAC_HW_FEATURE1		0x00000120
 #define XGMAC_HWFEAT_TSOEN		BIT(18)
+#define XGMAC_HWFEAT_ADDR64		GENMASK(15, 14)
 #define XGMAC_HWFEAT_TXFIFOSIZE		GENMASK(10, 6)
 #define XGMAC_HWFEAT_RXFIFOSIZE		GENMASK(4, 0)
 #define XGMAC_HW_FEATURE2		0x00000124
@@ -172,6 +173,7 @@
 #define XGMAC_EN_LPI			BIT(15)
 #define XGMAC_LPI_XIT_PKT		BIT(14)
 #define XGMAC_AAL			BIT(12)
+#define XGMAC_EAME			BIT(11)
 #define XGMAC_BLEN			GENMASK(7, 1)
 #define XGMAC_BLEN256			BIT(7)
 #define XGMAC_BLEN128			BIT(6)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c
index 98fa471da7c0..c4c45402b8f8 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c
@@ -242,8 +242,8 @@ static void dwxgmac2_get_addr(struct dma_desc *p, unsigned int *addr)
 
 static void dwxgmac2_set_addr(struct dma_desc *p, dma_addr_t addr)
 {
-	p->des0 = cpu_to_le32(addr);
-	p->des1 = 0;
+	p->des0 = cpu_to_le32(lower_32_bits(addr));
+	p->des1 = cpu_to_le32(upper_32_bits(addr));
 }
 
 static void dwxgmac2_clear(struct dma_desc *p)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
index 3f84271da836..08f3ed675a39 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
@@ -27,7 +27,7 @@ static void dwxgmac2_dma_init(void __iomem *ioaddr,
 	if (dma_cfg->aal)
 		value |= XGMAC_AAL;
 
-	writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
+	writel(value | XGMAC_EAME, ioaddr + XGMAC_DMA_SYSBUS_MODE);
 }
 
 static void dwxgmac2_dma_init_chan(void __iomem *ioaddr,
@@ -361,6 +361,23 @@ static void dwxgmac2_get_hw_feature(void __iomem *ioaddr,
 	/* MAC HW feature 1 */
 	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE1);
 	dma_cap->tsoen = (hw_cap & XGMAC_HWFEAT_TSOEN) >> 18;
+
+	dma_cap->addr64 = (hw_cap & XGMAC_HWFEAT_ADDR64) >> 14;
+	switch (dma_cap->addr64) {
+	case 0:
+		dma_cap->addr64 = 32;
+		break;
+	case 1:
+		dma_cap->addr64 = 40;
+		break;
+	case 2:
+		dma_cap->addr64 = 48;
+		break;
+	default:
+		dma_cap->addr64 = 32;
+		break;
+	}
+
 	dma_cap->tx_fifo_size =
 		128 << ((hw_cap & XGMAC_HWFEAT_TXFIFOSIZE) >> 6);
 	dma_cap->rx_fifo_size =
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 3a6fac22854e..65ff2a2a15e4 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -2768,7 +2768,7 @@ static int stmmac_release(struct net_device *dev)
  *  This function fills descriptor and request new descriptors according to
  *  buffer length to fill
  */
-static void stmmac_tso_allocator(struct stmmac_priv *priv, unsigned int des,
+static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des,
 				 int total_len, bool last_segment, u32 queue)
 {
 	struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
@@ -2779,11 +2779,18 @@ static void stmmac_tso_allocator(struct stmmac_priv *priv, unsigned int des,
 	tmp_len = total_len;
 
 	while (tmp_len > 0) {
+		dma_addr_t curr_addr;
+
 		tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
 		WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
 		desc = tx_q->dma_tx + tx_q->cur_tx;
 
-		desc->des0 = cpu_to_le32(des + (total_len - tmp_len));
+		curr_addr = des + (total_len - tmp_len);
+		if (priv->dma_cap.addr64 <= 32)
+			desc->des0 = cpu_to_le32(curr_addr);
+		else
+			stmmac_set_desc_addr(priv, desc, curr_addr);
+
 		buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
 			    TSO_MAX_BUFF_SIZE : tmp_len;
 
@@ -2829,11 +2836,12 @@ static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
 	struct stmmac_priv *priv = netdev_priv(dev);
 	int nfrags = skb_shinfo(skb)->nr_frags;
 	u32 queue = skb_get_queue_mapping(skb);
-	unsigned int first_entry, des;
+	unsigned int first_entry;
 	struct stmmac_tx_queue *tx_q;
 	int tmp_pay_len = 0;
 	u32 pay_len, mss;
 	u8 proto_hdr_len;
+	dma_addr_t des;
 	int i;
 
 	tx_q = &priv->tx_queue[queue];
@@ -2890,14 +2898,19 @@ static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
 	tx_q->tx_skbuff_dma[first_entry].buf = des;
 	tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
 
-	first->des0 = cpu_to_le32(des);
+	if (priv->dma_cap.addr64 <= 32) {
+		first->des0 = cpu_to_le32(des);
 
-	/* Fill start of payload in buff2 of first descriptor */
-	if (pay_len)
-		first->des1 = cpu_to_le32(des + proto_hdr_len);
+		/* Fill start of payload in buff2 of first descriptor */
+		if (pay_len)
+			first->des1 = cpu_to_le32(des + proto_hdr_len);
 
-	/* If needed take extra descriptors to fill the remaining payload */
-	tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
+		/* If needed take extra descriptors to fill the remaining payload */
+		tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
+	} else {
+		stmmac_set_desc_addr(priv, first, des);
+		tmp_pay_len = pay_len;
+	}
 
 	stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue);
 
@@ -3024,12 +3037,12 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
 	int i, csum_insertion = 0, is_jumbo = 0;
 	u32 queue = skb_get_queue_mapping(skb);
 	int nfrags = skb_shinfo(skb)->nr_frags;
-	int entry;
-	unsigned int first_entry;
 	struct dma_desc *desc, *first;
 	struct stmmac_tx_queue *tx_q;
+	unsigned int first_entry;
 	unsigned int enh_desc;
-	unsigned int des;
+	dma_addr_t des;
+	int entry;
 
 	tx_q = &priv->tx_queue[queue];
 
@@ -4306,6 +4319,15 @@ int stmmac_dvr_probe(struct device *device,
 		priv->tso = true;
 		dev_info(priv->device, "TSO feature enabled\n");
 	}
+
+	if (priv->dma_cap.addr64) {
+		ret = dma_set_mask_and_coherent(device,
+				DMA_BIT_MASK(priv->dma_cap.addr64));
+		if (!ret)
+			dev_info(priv->device, "Using %d bits DMA width\n",
+				 priv->dma_cap.addr64);
+	}
+
 	ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
 	ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
 #ifdef STMMAC_VLAN_TAG_USED
-- 
2.7.4


^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH net-next 08/10] net: stmmac: Update RX Tail Pointer to last free entry
  2019-06-26 13:47 [PATCH net-next 00/10] net: stmmac: 10GbE using XGMAC Jose Abreu
                   ` (6 preceding siblings ...)
  2019-06-26 13:47 ` [PATCH net-next 07/10] net: stmmac: Enable support for > 32 Bits addressing in XGMAC Jose Abreu
@ 2019-06-26 13:47 ` Jose Abreu
  2019-06-26 13:47 ` [PATCH net-next 09/10] net: stmmac: Only disable interrupts if NAPI is scheduled Jose Abreu
  2019-06-26 13:47 ` [PATCH net-next 10/10] net: stmmac: Try to get C45 PHY if everything else fails Jose Abreu
  9 siblings, 0 replies; 20+ messages in thread
From: Jose Abreu @ 2019-06-26 13:47 UTC (permalink / raw)
  To: linux-kernel, netdev
  Cc: Jose Abreu, Joao Pinto, David S . Miller, Giuseppe Cavallaro,
	Alexandre Torgue

Update the RX Tail Pointer to the last available SKB entry.

Signed-off-by: Jose Abreu <joabreu@synopsys.com>
Cc: Joao Pinto <jpinto@synopsys.com>
Cc: David S. Miller <davem@davemloft.net>
Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
---
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 65ff2a2a15e4..0893af8b432d 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -3337,6 +3337,8 @@ static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
 		entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE);
 	}
 	rx_q->dirty_rx = entry;
+	rx_q->rx_tail_addr = rx_q->dma_rx_phy +
+			    (rx_q->dirty_rx * sizeof(struct dma_desc));
 	stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
 }
 
-- 
2.7.4


^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH net-next 09/10] net: stmmac: Only disable interrupts if NAPI is scheduled
  2019-06-26 13:47 [PATCH net-next 00/10] net: stmmac: 10GbE using XGMAC Jose Abreu
                   ` (7 preceding siblings ...)
  2019-06-26 13:47 ` [PATCH net-next 08/10] net: stmmac: Update RX Tail Pointer to last free entry Jose Abreu
@ 2019-06-26 13:47 ` Jose Abreu
  2019-06-26 13:47 ` [PATCH net-next 10/10] net: stmmac: Try to get C45 PHY if everything else fails Jose Abreu
  9 siblings, 0 replies; 20+ messages in thread
From: Jose Abreu @ 2019-06-26 13:47 UTC (permalink / raw)
  To: linux-kernel, netdev
  Cc: Jose Abreu, Joao Pinto, David S . Miller, Giuseppe Cavallaro,
	Alexandre Torgue

Only disable the interrupts if RX NAPI gets to be scheduled. Also,
schedule the TX NAPI only when the interrupts are disabled.

Signed-off-by: Jose Abreu <joabreu@synopsys.com>
Cc: Joao Pinto <jpinto@synopsys.com>
Cc: David S. Miller <davem@davemloft.net>
Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
---
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 0893af8b432d..bc949665c529 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -2049,12 +2049,12 @@ static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan)
 						 &priv->xstats, chan);
 	struct stmmac_channel *ch = &priv->channel[chan];
 
-	if (status)
-		status |= handle_rx | handle_tx;
-
 	if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) {
-		stmmac_disable_dma_irq(priv, priv->ioaddr, chan);
-		napi_schedule_irqoff(&ch->rx_napi);
+		if (napi_schedule_prep(&ch->rx_napi)) {
+			stmmac_disable_dma_irq(priv, priv->ioaddr, chan);
+			__napi_schedule_irqoff(&ch->rx_napi);
+			status |= handle_tx;
+		}
 	}
 
 	if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use))
-- 
2.7.4


^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH net-next 10/10] net: stmmac: Try to get C45 PHY if everything else fails
  2019-06-26 13:47 [PATCH net-next 00/10] net: stmmac: 10GbE using XGMAC Jose Abreu
                   ` (8 preceding siblings ...)
  2019-06-26 13:47 ` [PATCH net-next 09/10] net: stmmac: Only disable interrupts if NAPI is scheduled Jose Abreu
@ 2019-06-26 13:47 ` Jose Abreu
  2019-06-26 20:01   ` Andrew Lunn
  9 siblings, 1 reply; 20+ messages in thread
From: Jose Abreu @ 2019-06-26 13:47 UTC (permalink / raw)
  To: linux-kernel, netdev
  Cc: Jose Abreu, Joao Pinto, David S . Miller, Giuseppe Cavallaro,
	Alexandre Torgue

On PCI based setups that are connected to C45 PHY we won't have DT
bindings specifying what's the correct PHY type.

Fallback to C45 if everything else fails when trying to acquire PHY.

Signed-off-by: Jose Abreu <joabreu@synopsys.com>
Cc: Joao Pinto <jpinto@synopsys.com>
Cc: David S. Miller <davem@davemloft.net>
Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
---
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index bc949665c529..e790ab79e819 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -1014,6 +1014,20 @@ static int stmmac_init_phy(struct net_device *dev)
 
 		phydev = mdiobus_get_phy(priv->mii, addr);
 		if (!phydev) {
+			/* Try C45 */
+			phydev = get_phy_device(priv->mii, addr, true);
+			if (phydev && !IS_ERR(phydev)) {
+				ret = phy_device_register(phydev);
+				if (ret) {
+					phy_device_free(phydev);
+					phydev = NULL;
+				}
+			} else {
+				phydev = NULL;
+			}
+		}
+
+		if (!phydev) {
 			netdev_err(priv->dev, "no phy at addr %d\n", addr);
 			return -ENODEV;
 		}
-- 
2.7.4


^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH net-next 01/10] net: stmmac: dwxgmac: Enable EDMA by default
  2019-06-26 13:47 ` [PATCH net-next 01/10] net: stmmac: dwxgmac: Enable EDMA by default Jose Abreu
@ 2019-06-26 16:33   ` David Miller
  0 siblings, 0 replies; 20+ messages in thread
From: David Miller @ 2019-06-26 16:33 UTC (permalink / raw)
  To: Jose.Abreu
  Cc: linux-kernel, netdev, Joao.Pinto, peppe.cavallaro, alexandre.torgue

From: Jose Abreu <Jose.Abreu@synopsys.com>
Date: Wed, 26 Jun 2019 15:47:35 +0200

> @@ -122,6 +122,8 @@ static void dwxgmac2_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
>  	}
>  
>  	writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
> +	writel(GENMASK(29, 0), ioaddr + XGMAC_TX_EDMA_CTRL);
> +	writel(GENMASK(29, 0), ioaddr + XGMAC_RX_EDMA_CTRL);
>  }

This mask is magic and there is no indication what the bits mean and
in particular what it means to set bits 0 -- 29

You have to document what these bits mean and thus what these register
writes actually do.

^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH net-next 10/10] net: stmmac: Try to get C45 PHY if everything else fails
  2019-06-26 13:47 ` [PATCH net-next 10/10] net: stmmac: Try to get C45 PHY if everything else fails Jose Abreu
@ 2019-06-26 20:01   ` Andrew Lunn
  2019-06-27  7:54     ` Jose Abreu
  0 siblings, 1 reply; 20+ messages in thread
From: Andrew Lunn @ 2019-06-26 20:01 UTC (permalink / raw)
  To: Jose Abreu
  Cc: linux-kernel, netdev, Joao Pinto, David S . Miller,
	Giuseppe Cavallaro, Alexandre Torgue

On Wed, Jun 26, 2019 at 03:47:44PM +0200, Jose Abreu wrote:
> On PCI based setups that are connected to C45 PHY we won't have DT
> bindings specifying what's the correct PHY type.

You can associate a DT node to a PCI device. The driver does not have
to do anything special, the PCI core code does all the work.

As an example look at imx6q-zii-rdu2.dts, node &pcie, which has an
intel i210 on the pcie bus, and we need a handle to it.

   Andrew

^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH net-next 07/10] net: stmmac: Enable support for > 32 Bits addressing in XGMAC
  2019-06-26 13:47 ` [PATCH net-next 07/10] net: stmmac: Enable support for > 32 Bits addressing in XGMAC Jose Abreu
@ 2019-06-26 20:19   ` Andrew Lunn
  2019-06-27  7:54     ` Jose Abreu
  0 siblings, 1 reply; 20+ messages in thread
From: Andrew Lunn @ 2019-06-26 20:19 UTC (permalink / raw)
  To: Jose Abreu
  Cc: linux-kernel, netdev, Joao Pinto, David S . Miller,
	Giuseppe Cavallaro, Alexandre Torgue

> +
> +	if (priv->dma_cap.addr64) {
> +		ret = dma_set_mask_and_coherent(device,
> +				DMA_BIT_MASK(priv->dma_cap.addr64));
> +		if (!ret)
> +			dev_info(priv->device, "Using %d bits DMA width\n",
> +				 priv->dma_cap.addr64);
> +	}

Hi Jose

If dma_set_mask_and_coherent() fails, i think you are supposed to fall
back to 32 bits. So you might want to clear priv->dma_cap.addr64.

But don't trust my, i could be wrong.

    Andrew

^ permalink raw reply	[flat|nested] 20+ messages in thread

* RE: [PATCH net-next 10/10] net: stmmac: Try to get C45 PHY if everything else fails
  2019-06-26 20:01   ` Andrew Lunn
@ 2019-06-27  7:54     ` Jose Abreu
  2019-06-27 13:23       ` Andrew Lunn
  0 siblings, 1 reply; 20+ messages in thread
From: Jose Abreu @ 2019-06-27  7:54 UTC (permalink / raw)
  To: Andrew Lunn, Jose Abreu
  Cc: linux-kernel, netdev, Joao Pinto, David S . Miller,
	Giuseppe Cavallaro, Alexandre Torgue

From: Andrew Lunn <andrew@lunn.ch>

> On Wed, Jun 26, 2019 at 03:47:44PM +0200, Jose Abreu wrote:
> > On PCI based setups that are connected to C45 PHY we won't have DT
> > bindings specifying what's the correct PHY type.
> 
> You can associate a DT node to a PCI device. The driver does not have
> to do anything special, the PCI core code does all the work.
> 
> As an example look at imx6q-zii-rdu2.dts, node &pcie, which has an
> intel i210 on the pcie bus, and we need a handle to it.

That's for ARM but I'm using X86_64 which only has ACPI :/

^ permalink raw reply	[flat|nested] 20+ messages in thread

* RE: [PATCH net-next 07/10] net: stmmac: Enable support for > 32 Bits addressing in XGMAC
  2019-06-26 20:19   ` Andrew Lunn
@ 2019-06-27  7:54     ` Jose Abreu
  0 siblings, 0 replies; 20+ messages in thread
From: Jose Abreu @ 2019-06-27  7:54 UTC (permalink / raw)
  To: Andrew Lunn, Jose Abreu
  Cc: linux-kernel, netdev, Joao Pinto, David S . Miller,
	Giuseppe Cavallaro, Alexandre Torgue

From: Andrew Lunn <andrew@lunn.ch>

> > +
> > +	if (priv->dma_cap.addr64) {
> > +		ret = dma_set_mask_and_coherent(device,
> > +				DMA_BIT_MASK(priv->dma_cap.addr64));
> > +		if (!ret)
> > +			dev_info(priv->device, "Using %d bits DMA width\n",
> > +				 priv->dma_cap.addr64);
> > +	}
> 
> Hi Jose
> 
> If dma_set_mask_and_coherent() fails, i think you are supposed to fall
> back to 32 bits. So you might want to clear priv->dma_cap.addr64.

Yeah, seems right. Thanks for pointing!

^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH net-next 10/10] net: stmmac: Try to get C45 PHY if everything else fails
  2019-06-27  7:54     ` Jose Abreu
@ 2019-06-27 13:23       ` Andrew Lunn
  2019-06-27 13:33         ` Jose Abreu
  0 siblings, 1 reply; 20+ messages in thread
From: Andrew Lunn @ 2019-06-27 13:23 UTC (permalink / raw)
  To: Jose Abreu
  Cc: linux-kernel, netdev, Joao Pinto, David S . Miller,
	Giuseppe Cavallaro, Alexandre Torgue

On Thu, Jun 27, 2019 at 07:54:14AM +0000, Jose Abreu wrote:
> From: Andrew Lunn <andrew@lunn.ch>
> 
> > On Wed, Jun 26, 2019 at 03:47:44PM +0200, Jose Abreu wrote:
> > > On PCI based setups that are connected to C45 PHY we won't have DT
> > > bindings specifying what's the correct PHY type.
> > 
> > You can associate a DT node to a PCI device. The driver does not have
> > to do anything special, the PCI core code does all the work.
> > 
> > As an example look at imx6q-zii-rdu2.dts, node &pcie, which has an
> > intel i210 on the pcie bus, and we need a handle to it.
> 
> That's for ARM but I'm using X86_64 which only has ACPI :/

Hi Jose

There have been some drivers gaining patches for ACPI. That is
probably the better long term solution, ask ACPI where is the PHY and
what MDIO protocol to use to talk to it.

	 Andrew

^ permalink raw reply	[flat|nested] 20+ messages in thread

* RE: [PATCH net-next 10/10] net: stmmac: Try to get C45 PHY if everything else fails
  2019-06-27 13:23       ` Andrew Lunn
@ 2019-06-27 13:33         ` Jose Abreu
  2019-06-27 14:03           ` Andrew Lunn
  0 siblings, 1 reply; 20+ messages in thread
From: Jose Abreu @ 2019-06-27 13:33 UTC (permalink / raw)
  To: Andrew Lunn, Jose Abreu
  Cc: linux-kernel, netdev, Joao Pinto, David S . Miller,
	Giuseppe Cavallaro, Alexandre Torgue

From: Andrew Lunn <andrew@lunn.ch>

> There have been some drivers gaining patches for ACPI. That is
> probably the better long term solution, ask ACPI where is the PHY and
> what MDIO protocol to use to talk to it.

Hmmm, I'm not sure this is going to work that way ...

My setup is a PCI EP which is hot-pluggable and as far as I know ACPI 
has only static content (????)

^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH net-next 10/10] net: stmmac: Try to get C45 PHY if everything else fails
  2019-06-27 13:33         ` Jose Abreu
@ 2019-06-27 14:03           ` Andrew Lunn
  2019-06-28  7:27             ` Jose Abreu
  0 siblings, 1 reply; 20+ messages in thread
From: Andrew Lunn @ 2019-06-27 14:03 UTC (permalink / raw)
  To: Jose Abreu
  Cc: linux-kernel, netdev, Joao Pinto, David S . Miller,
	Giuseppe Cavallaro, Alexandre Torgue

On Thu, Jun 27, 2019 at 01:33:59PM +0000, Jose Abreu wrote:
> From: Andrew Lunn <andrew@lunn.ch>
> 
> > There have been some drivers gaining patches for ACPI. That is
> > probably the better long term solution, ask ACPI where is the PHY and
> > what MDIO protocol to use to talk to it.
> 
> Hmmm, I'm not sure this is going to work that way ...
> 
> My setup is a PCI EP which is hot-pluggable and as far as I know ACPI 
> has only static content (????)

I've wanted to improve the PHY probe code for a while. I was thinking
we should add a flag to the MDIO bus driver structure indicating it
can do C45. When that flag is present, we should also scan the bus for
C45 devices, and register them as well.

With that in place, i think your problem goes away. Architecturally, i
think it is wrong that a MAC driver is registering PHY devices. The
MDIO core should do this.

      Andrew

^ permalink raw reply	[flat|nested] 20+ messages in thread

* RE: [PATCH net-next 10/10] net: stmmac: Try to get C45 PHY if everything else fails
  2019-06-27 14:03           ` Andrew Lunn
@ 2019-06-28  7:27             ` Jose Abreu
  0 siblings, 0 replies; 20+ messages in thread
From: Jose Abreu @ 2019-06-28  7:27 UTC (permalink / raw)
  To: Andrew Lunn, Jose Abreu
  Cc: linux-kernel, netdev, Joao Pinto, David S . Miller,
	Giuseppe Cavallaro, Alexandre Torgue

From: Andrew Lunn <andrew@lunn.ch>

> On Thu, Jun 27, 2019 at 01:33:59PM +0000, Jose Abreu wrote:
> > From: Andrew Lunn <andrew@lunn.ch>
> > 
> > > There have been some drivers gaining patches for ACPI. That is
> > > probably the better long term solution, ask ACPI where is the PHY and
> > > what MDIO protocol to use to talk to it.
> > 
> > Hmmm, I'm not sure this is going to work that way ...
> > 
> > My setup is a PCI EP which is hot-pluggable and as far as I know ACPI 
> > has only static content (????)
> 
> I've wanted to improve the PHY probe code for a while. I was thinking
> we should add a flag to the MDIO bus driver structure indicating it
> can do C45. When that flag is present, we should also scan the bus for
> C45 devices, and register them as well.
> 
> With that in place, i think your problem goes away. Architecturally, i
> think it is wrong that a MAC driver is registering PHY devices. The
> MDIO core should do this.

Ok, I will drop this patch from the series until we come up with a 
better solution.

^ permalink raw reply	[flat|nested] 20+ messages in thread

end of thread, back to index

Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-06-26 13:47 [PATCH net-next 00/10] net: stmmac: 10GbE using XGMAC Jose Abreu
2019-06-26 13:47 ` [PATCH net-next 01/10] net: stmmac: dwxgmac: Enable EDMA by default Jose Abreu
2019-06-26 16:33   ` David Miller
2019-06-26 13:47 ` [PATCH net-next 02/10] net: stmmac: Do not try to enable PHY EEE if MAC does not support it Jose Abreu
2019-06-26 13:47 ` [PATCH net-next 03/10] net: stmmac: Decrease default RX Watchdog value Jose Abreu
2019-06-26 13:47 ` [PATCH net-next 04/10] net: stmmac: dwxgmac: Fix the undefined burst setting Jose Abreu
2019-06-26 13:47 ` [PATCH net-next 05/10] net: stmmac: Add the missing speeds that XGMAC supports Jose Abreu
2019-06-26 13:47 ` [PATCH net-next 06/10] net: stmmac: Do not disable interrupts when cleaning TX Jose Abreu
2019-06-26 13:47 ` [PATCH net-next 07/10] net: stmmac: Enable support for > 32 Bits addressing in XGMAC Jose Abreu
2019-06-26 20:19   ` Andrew Lunn
2019-06-27  7:54     ` Jose Abreu
2019-06-26 13:47 ` [PATCH net-next 08/10] net: stmmac: Update RX Tail Pointer to last free entry Jose Abreu
2019-06-26 13:47 ` [PATCH net-next 09/10] net: stmmac: Only disable interrupts if NAPI is scheduled Jose Abreu
2019-06-26 13:47 ` [PATCH net-next 10/10] net: stmmac: Try to get C45 PHY if everything else fails Jose Abreu
2019-06-26 20:01   ` Andrew Lunn
2019-06-27  7:54     ` Jose Abreu
2019-06-27 13:23       ` Andrew Lunn
2019-06-27 13:33         ` Jose Abreu
2019-06-27 14:03           ` Andrew Lunn
2019-06-28  7:27             ` Jose Abreu

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