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From: Alexandru Ardelean <alexandru.ardelean@analog.com>
To: <netdev@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>
Cc: <davem@davemloft.net>, <robh+dt@kernel.org>,
	<mark.rutland@arm.com>, <f.fainelli@gmail.com>,
	<hkallweit1@gmail.com>, <andrew@lunn.ch>,
	Alexandru Ardelean <alexandru.ardelean@analog.com>
Subject: [PATCH v5 10/13] net: phy: adin: implement PHY subsystem software reset
Date: Fri, 16 Aug 2019 16:10:08 +0300
Message-ID: <20190816131011.23264-11-alexandru.ardelean@analog.com> (raw)
In-Reply-To: <20190816131011.23264-1-alexandru.ardelean@analog.com>

The ADIN PHYs supports 4 types of reset:
1. The standard PHY reset via BMCR_RESET bit in MII_BMCR reg
2. Reset via GPIO
3. Reset via reg GeSftRst (0xff0c) & reload previous pin configs
4. Reset via reg GeSftRst (0xff0c) & request new pin configs

Resets 2, 3 & 4 are almost identical, with the exception that the crystal
oscillator is available during reset for 2.

This change implements subsystem software reset via the GeSftRst and
reloading the previous pin configuration (so reset number 3).
This will also reset the PHY core regs (similar to reset 1).

Since writing bit 1 to reg GeSftRst is self-clearing, the only thing that
can be done, is to write to that register, wait a specific amount of time
(10 milliseconds should be enough) and try to read back and check if there
are no errors on read. A busy-wait-read won't work well, and may sometimes
work or not work.

In case phylib is configured to also do a reset via GPIO, the ADIN PHY may
be reset twice when the PHY device registers, but that isn't a problem,
since it's being done on boot (or PHY device register).

Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
---
 drivers/net/phy/adin.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c
index 131b7f85ae32..5622a393e7cf 100644
--- a/drivers/net/phy/adin.c
+++ b/drivers/net/phy/adin.c
@@ -6,6 +6,7 @@
  */
 #include <linux/kernel.h>
 #include <linux/bitfield.h>
+#include <linux/delay.h>
 #include <linux/errno.h>
 #include <linux/init.h>
 #include <linux/module.h>
@@ -50,6 +51,9 @@
 #define ADIN1300_CLOCK_STOP_REG			0x9400
 #define ADIN1300_LPI_WAKE_ERR_CNT_REG		0xa000
 
+#define ADIN1300_GE_SOFT_RESET_REG		0xff0c
+#define   ADIN1300_GE_SOFT_RESET		BIT(0)
+
 #define ADIN1300_GE_RGMII_CFG_REG		0xff23
 #define   ADIN1300_GE_RGMII_RX_MSK		GENMASK(8, 6)
 #define   ADIN1300_GE_RGMII_RX_SEL(x)		\
@@ -442,11 +446,32 @@ static int adin_read_status(struct phy_device *phydev)
 	return genphy_read_status(phydev);
 }
 
+static int adin_soft_reset(struct phy_device *phydev)
+{
+	int rc;
+
+	/* The reset bit is self-clearing, set it and wait */
+	rc = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
+			      ADIN1300_GE_SOFT_RESET_REG,
+			      ADIN1300_GE_SOFT_RESET);
+	if (rc < 0)
+		return rc;
+
+	msleep(10);
+
+	/* If we get a read error something may be wrong */
+	rc = phy_read_mmd(phydev, MDIO_MMD_VEND1,
+			  ADIN1300_GE_SOFT_RESET_REG);
+
+	return rc < 0 ? rc : 0;
+}
+
 static struct phy_driver adin_driver[] = {
 	{
 		PHY_ID_MATCH_MODEL(PHY_ID_ADIN1200),
 		.name		= "ADIN1200",
 		.config_init	= adin_config_init,
+		.soft_reset	= adin_soft_reset,
 		.config_aneg	= adin_config_aneg,
 		.read_status	= adin_read_status,
 		.ack_interrupt	= adin_phy_ack_intr,
@@ -460,6 +485,7 @@ static struct phy_driver adin_driver[] = {
 		PHY_ID_MATCH_MODEL(PHY_ID_ADIN1300),
 		.name		= "ADIN1300",
 		.config_init	= adin_config_init,
+		.soft_reset	= adin_soft_reset,
 		.config_aneg	= adin_config_aneg,
 		.read_status	= adin_read_status,
 		.ack_interrupt	= adin_phy_ack_intr,
-- 
2.20.1


  parent reply index

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-16 13:09 [PATCH v5 00/13] net: phy: adin: add support for Analog Devices PHYs Alexandru Ardelean
2019-08-16 13:09 ` [PATCH v5 01/13] " Alexandru Ardelean
2019-08-16 13:10 ` [PATCH v5 02/13] net: phy: adin: hook genphy_{suspend,resume} into the driver Alexandru Ardelean
2019-08-16 13:10 ` [PATCH v5 03/13] net: phy: adin: add support for interrupts Alexandru Ardelean
2019-08-16 13:10 ` [PATCH v5 04/13] net: phy: adin: add {write,read}_mmd hooks Alexandru Ardelean
2019-08-16 13:10 ` [PATCH v5 05/13] net: phy: adin: configure RGMII/RMII/MII modes on config Alexandru Ardelean
2019-08-16 13:10 ` [PATCH v5 06/13] net: phy: adin: make RGMII internal delays configurable Alexandru Ardelean
2019-08-16 13:10 ` [PATCH v5 07/13] net: phy: adin: make RMII fifo depth configurable Alexandru Ardelean
2019-08-16 13:10 ` [PATCH v5 08/13] net: phy: adin: add support MDI/MDIX/Auto-MDI selection Alexandru Ardelean
2019-08-16 13:10 ` [PATCH v5 09/13] net: phy: adin: add EEE translation layer from Clause 45 to Clause 22 Alexandru Ardelean
2019-08-16 13:10 ` Alexandru Ardelean [this message]
2019-08-16 13:19   ` [PATCH v5 10/13] net: phy: adin: implement PHY subsystem software reset Andrew Lunn
2019-08-16 13:10 ` [PATCH v5 11/13] net: phy: adin: implement downshift configuration via phy-tunable Alexandru Ardelean
2019-08-16 13:10 ` [PATCH v5 12/13] net: phy: adin: add ethtool get_stats support Alexandru Ardelean
2019-08-16 13:24   ` Andrew Lunn
2019-08-16 13:10 ` [PATCH v5 13/13] dt-bindings: net: add bindings for ADIN PHY driver Alexandru Ardelean
2019-08-16 18:57 ` [PATCH v5 00/13] net: phy: adin: add support for Analog Devices PHYs David Miller

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