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Received: from nwd2mta2.analog.com (137.71.25.57) by SN1NAM02FT062.mail.protection.outlook.com (10.152.72.208) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.20.2178.16 via Frontend Transport; Fri, 16 Aug 2019 13:10:44 +0000 Received: from NWD2HUBCAS7.ad.analog.com (nwd2hubcas7.ad.analog.com [10.64.69.107]) by nwd2mta2.analog.com (8.13.8/8.13.8) with ESMTP id x7GDAhO0007931 (version=TLSv1/SSLv3 cipher=AES256-SHA bits=256 verify=OK); Fri, 16 Aug 2019 06:10:43 -0700 Received: from saturn.ad.analog.com (10.48.65.113) by NWD2HUBCAS7.ad.analog.com (10.64.69.107) with Microsoft SMTP Server id 14.3.408.0; Fri, 16 Aug 2019 09:10:43 -0400 From: Alexandru Ardelean To: , , CC: , , , , , , Alexandru Ardelean Subject: [PATCH v5 10/13] net: phy: adin: implement PHY subsystem software reset Date: Fri, 16 Aug 2019 16:10:08 +0300 Message-ID: <20190816131011.23264-11-alexandru.ardelean@analog.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190816131011.23264-1-alexandru.ardelean@analog.com> References: <20190816131011.23264-1-alexandru.ardelean@analog.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ADIRoutedOnPrem: True X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:137.71.25.57;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(39860400002)(396003)(136003)(346002)(376002)(2980300002)(189003)(199004)(107886003)(2870700001)(70586007)(5660300002)(70206006)(186003)(426003)(4326008)(356004)(2906002)(6666004)(126002)(478600001)(476003)(446003)(2616005)(486006)(1076003)(44832011)(11346002)(110136005)(316002)(26005)(106002)(54906003)(336012)(36756003)(305945005)(51416003)(7636002)(48376002)(50466002)(2201001)(76176011)(8676002)(8936002)(14444005)(246002)(47776003)(7696005)(50226002)(86362001);DIR:OUT;SFP:1101;SCL:1;SRVR:MWHPR03MB2845;H:nwd2mta2.analog.com;FPR:;SPF:Pass;LANG:en;PTR:nwd2mail11.analog.com;MX:1;A:1; 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The standard PHY reset via BMCR_RESET bit in MII_BMCR reg 2. Reset via GPIO 3. Reset via reg GeSftRst (0xff0c) & reload previous pin configs 4. Reset via reg GeSftRst (0xff0c) & request new pin configs Resets 2, 3 & 4 are almost identical, with the exception that the crystal oscillator is available during reset for 2. This change implements subsystem software reset via the GeSftRst and reloading the previous pin configuration (so reset number 3). This will also reset the PHY core regs (similar to reset 1). Since writing bit 1 to reg GeSftRst is self-clearing, the only thing that can be done, is to write to that register, wait a specific amount of time (10 milliseconds should be enough) and try to read back and check if there are no errors on read. A busy-wait-read won't work well, and may sometimes work or not work. In case phylib is configured to also do a reset via GPIO, the ADIN PHY may be reset twice when the PHY device registers, but that isn't a problem, since it's being done on boot (or PHY device register). Signed-off-by: Alexandru Ardelean --- drivers/net/phy/adin.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c index 131b7f85ae32..5622a393e7cf 100644 --- a/drivers/net/phy/adin.c +++ b/drivers/net/phy/adin.c @@ -6,6 +6,7 @@ */ #include #include +#include #include #include #include @@ -50,6 +51,9 @@ #define ADIN1300_CLOCK_STOP_REG 0x9400 #define ADIN1300_LPI_WAKE_ERR_CNT_REG 0xa000 +#define ADIN1300_GE_SOFT_RESET_REG 0xff0c +#define ADIN1300_GE_SOFT_RESET BIT(0) + #define ADIN1300_GE_RGMII_CFG_REG 0xff23 #define ADIN1300_GE_RGMII_RX_MSK GENMASK(8, 6) #define ADIN1300_GE_RGMII_RX_SEL(x) \ @@ -442,11 +446,32 @@ static int adin_read_status(struct phy_device *phydev) return genphy_read_status(phydev); } +static int adin_soft_reset(struct phy_device *phydev) +{ + int rc; + + /* The reset bit is self-clearing, set it and wait */ + rc = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, + ADIN1300_GE_SOFT_RESET_REG, + ADIN1300_GE_SOFT_RESET); + if (rc < 0) + return rc; + + msleep(10); + + /* If we get a read error something may be wrong */ + rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, + ADIN1300_GE_SOFT_RESET_REG); + + return rc < 0 ? rc : 0; +} + static struct phy_driver adin_driver[] = { { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1200), .name = "ADIN1200", .config_init = adin_config_init, + .soft_reset = adin_soft_reset, .config_aneg = adin_config_aneg, .read_status = adin_read_status, .ack_interrupt = adin_phy_ack_intr, @@ -460,6 +485,7 @@ static struct phy_driver adin_driver[] = { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1300), .name = "ADIN1300", .config_init = adin_config_init, + .soft_reset = adin_soft_reset, .config_aneg = adin_config_aneg, .read_status = adin_read_status, .ack_interrupt = adin_phy_ack_intr, -- 2.20.1