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[94.113.220.175]) by smtp.gmail.com with ESMTPSA id p15sm5277565wmb.10.2019.11.08.14.21.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Nov 2019 14:21:59 -0800 (PST) Date: Fri, 8 Nov 2019 23:21:59 +0100 From: Jiri Pirko To: Jakub Kicinski Cc: Parav Pandit , alex.williamson@redhat.com, davem@davemloft.net, kvm@vger.kernel.org, netdev@vger.kernel.org, saeedm@mellanox.com, kwankhede@nvidia.com, leon@kernel.org, cohuck@redhat.com, jiri@mellanox.com, linux-rdma@vger.kernel.org, Or Gerlitz Subject: Re: [PATCH net-next 00/19] Mellanox, mlx5 sub function support Message-ID: <20191108222159.GA6990@nanopsycho> References: <20191107160448.20962-1-parav@mellanox.com> <20191107153234.0d735c1f@cakuba.netronome.com> <20191108121233.GJ6990@nanopsycho> <20191108110640.225b2724@cakuba> <20191108194118.GY6990@nanopsycho> <20191108132120.510d8b87@cakuba> <20191108213952.GZ6990@nanopsycho> <20191108135109.0c833847@cakuba> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191108135109.0c833847@cakuba> User-Agent: Mutt/1.12.1 (2019-06-15) Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Fri, Nov 08, 2019 at 10:51:09PM CET, jakub.kicinski@netronome.com wrote: >On Fri, 8 Nov 2019 22:39:52 +0100, Jiri Pirko wrote: >> >> Please let me understand how your device is different. >> >> Originally Parav didn't want to have mlx5 subfunctions as mdev. He >> >> wanted to have them tight to the same pci device as the pf. No >> >> difference from what you describe you want. However while we thought >> >> about how to fit things in, how to handle na phys_port_name, how to see >> >> things in sysfs we came up with an idea of a dedicated bus. >> > >> >The difference is that there is naturally a main device and subslices >> >with this new mlx5 code. In mlx4 or nfp all ports are equal and >> >statically allocated when FW initializes based on port breakout. >> >> Ah, I see. I was missing the static part in nfp. Now I understand. It is >> just an another "pf", but not real pf in the pci terminology, right? > >Ack, due to (real and perceived) HW limitations what should have been >separate PFs got squished into a single big one. > >Biggest NFP chip has an insane (for a NIC) number Ethernet ports. Okay. So we'll endup in having flavour "mdev" for the SFs that are spawned on fly by user and "sf" for the fixed one - that is your patchset if I recall correctly.