* [PATCH] net: phy: dp83867: Set FORCE_LINK_GOOD do default after reset
@ 2020-01-14 11:24 Michael Grzeschik
2020-01-14 13:25 ` Andrew Lunn
0 siblings, 1 reply; 9+ messages in thread
From: Michael Grzeschik @ 2020-01-14 11:24 UTC (permalink / raw)
To: netdev; +Cc: andrew, f.fainelli, hkallweit1, kernel
According to the Datasheet this bit should be 0 (Normal operation) in
default. With the FORCE_LINK_GOOD bit set, it is not possible to get a
link. This patch sets FORCE_LINK_GOOD to the default value after
resetting the phy.
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
---
drivers/net/phy/dp83867.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index adda0d0eab800..60a09fabf41d1 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -99,6 +99,7 @@
#define DP83867_PHYCR_TX_FIFO_DEPTH_MASK GENMASK(15, 14)
#define DP83867_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12)
#define DP83867_PHYCR_RESERVED_MASK BIT(11)
+#define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10)
/* RGMIIDCTL bits */
#define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf
@@ -627,7 +628,7 @@ static int dp83867_config_init(struct phy_device *phydev)
static int dp83867_phy_reset(struct phy_device *phydev)
{
- int err;
+ int val, err;
err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
if (err < 0)
@@ -635,6 +636,16 @@ static int dp83867_phy_reset(struct phy_device *phydev)
usleep_range(10, 20);
+ /* After reset FORCE_LINK_GOOD bit is set. Although the
+ * default value should be unset. Disable FORCE_LINK_GOOD
+ * for the phy to work properly.
+ */
+ val = phy_read(phydev, MII_DP83867_PHYCTRL);
+ if (val & DP83867_PHYCR_FORCE_LINK_GOOD) {
+ val &= ~(DP83867_PHYCR_FORCE_LINK_GOOD);
+ phy_write(phydev, MII_DP83867_PHYCTRL, val);
+ }
+
return 0;
}
--
2.25.0.rc1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH] net: phy: dp83867: Set FORCE_LINK_GOOD do default after reset
2020-01-14 11:24 [PATCH] net: phy: dp83867: Set FORCE_LINK_GOOD do default after reset Michael Grzeschik
@ 2020-01-14 13:25 ` Andrew Lunn
2020-01-14 16:45 ` [PATCH v2] net: phy: dp83867: Set FORCE_LINK_GOOD to " Michael Grzeschik
0 siblings, 1 reply; 9+ messages in thread
From: Andrew Lunn @ 2020-01-14 13:25 UTC (permalink / raw)
To: Michael Grzeschik; +Cc: netdev, f.fainelli, hkallweit1, kernel
Hi Michael
> @@ -635,6 +636,16 @@ static int dp83867_phy_reset(struct phy_device *phydev)
>
> usleep_range(10, 20);
>
> + /* After reset FORCE_LINK_GOOD bit is set. Although the
> + * default value should be unset. Disable FORCE_LINK_GOOD
> + * for the phy to work properly.
> + */
> + val = phy_read(phydev, MII_DP83867_PHYCTRL);
> + if (val & DP83867_PHYCR_FORCE_LINK_GOOD) {
> + val &= ~(DP83867_PHYCR_FORCE_LINK_GOOD);
> + phy_write(phydev, MII_DP83867_PHYCTRL, val);
> + }
You could use phy_modify().
Andrew
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH v2] net: phy: dp83867: Set FORCE_LINK_GOOD to default after reset
2020-01-14 13:25 ` Andrew Lunn
@ 2020-01-14 16:45 ` Michael Grzeschik
2020-01-14 19:21 ` Heiner Kallweit
0 siblings, 1 reply; 9+ messages in thread
From: Michael Grzeschik @ 2020-01-14 16:45 UTC (permalink / raw)
To: netdev; +Cc: andrew, f.fainelli, hkallweit1, kernel
According to the Datasheet this bit should be 0 (Normal operation) in
default. With the FORCE_LINK_GOOD bit set, it is not possible to get a
link. This patch sets FORCE_LINK_GOOD to the default value after
resetting the phy.
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
---
v1 -> v2: - fixed typo in subject line
- used phy_modify instead of read/write
drivers/net/phy/dp83867.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index adda0d0eab800..68855177d92cc 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -99,6 +99,7 @@
#define DP83867_PHYCR_TX_FIFO_DEPTH_MASK GENMASK(15, 14)
#define DP83867_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12)
#define DP83867_PHYCR_RESERVED_MASK BIT(11)
+#define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10)
/* RGMIIDCTL bits */
#define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf
@@ -635,6 +636,15 @@ static int dp83867_phy_reset(struct phy_device *phydev)
usleep_range(10, 20);
+ /* After reset FORCE_LINK_GOOD bit is set. Although the
+ * default value should be unset. Disable FORCE_LINK_GOOD
+ * for the phy to work properly.
+ */
+ err = phy_modify(phydev, MII_DP83867_PHYCTRL,
+ DP83867_PHYCR_FORCE_LINK_GOOD, 0);
+ if (err < 0)
+ return err;
+
return 0;
}
--
2.25.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v2] net: phy: dp83867: Set FORCE_LINK_GOOD to default after reset
2020-01-14 16:45 ` [PATCH v2] net: phy: dp83867: Set FORCE_LINK_GOOD to " Michael Grzeschik
@ 2020-01-14 19:21 ` Heiner Kallweit
2020-01-15 8:01 ` [PATCH v3] " Michael Grzeschik
0 siblings, 1 reply; 9+ messages in thread
From: Heiner Kallweit @ 2020-01-14 19:21 UTC (permalink / raw)
To: Michael Grzeschik, netdev; +Cc: andrew, f.fainelli, kernel
On 14.01.2020 17:45, Michael Grzeschik wrote:
> According to the Datasheet this bit should be 0 (Normal operation) in
> default. With the FORCE_LINK_GOOD bit set, it is not possible to get a
> link. This patch sets FORCE_LINK_GOOD to the default value after
> resetting the phy.
>
> Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
> ---
> v1 -> v2: - fixed typo in subject line
> - used phy_modify instead of read/write
>
> drivers/net/phy/dp83867.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
> index adda0d0eab800..68855177d92cc 100644
> --- a/drivers/net/phy/dp83867.c
> +++ b/drivers/net/phy/dp83867.c
> @@ -99,6 +99,7 @@
> #define DP83867_PHYCR_TX_FIFO_DEPTH_MASK GENMASK(15, 14)
> #define DP83867_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12)
> #define DP83867_PHYCR_RESERVED_MASK BIT(11)
> +#define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10)
>
> /* RGMIIDCTL bits */
> #define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf
> @@ -635,6 +636,15 @@ static int dp83867_phy_reset(struct phy_device *phydev)
>
> usleep_range(10, 20);
>
> + /* After reset FORCE_LINK_GOOD bit is set. Although the
> + * default value should be unset. Disable FORCE_LINK_GOOD
> + * for the phy to work properly.
> + */
> + err = phy_modify(phydev, MII_DP83867_PHYCTRL,
> + DP83867_PHYCR_FORCE_LINK_GOOD, 0);
> + if (err < 0)
> + return err;
> +
> return 0;
You can simply do "return phy_modify();" here.
> }
>
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3] net: phy: dp83867: Set FORCE_LINK_GOOD to default after reset
2020-01-14 19:21 ` Heiner Kallweit
@ 2020-01-15 8:01 ` Michael Grzeschik
2020-01-16 12:57 ` David Miller
0 siblings, 1 reply; 9+ messages in thread
From: Michael Grzeschik @ 2020-01-15 8:01 UTC (permalink / raw)
To: netdev; +Cc: andrew, f.fainelli, hkallweit1, kernel
According to the Datasheet this bit should be 0 (Normal operation) in
default. With the FORCE_LINK_GOOD bit set, it is not possible to get a
link. This patch sets FORCE_LINK_GOOD to the default value after
resetting the phy.
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
---
v1 -> v2: - fixed typo in subject line
- used phy_modify instead of read/write
v2 -> v3: - returned dp83867_phy_reset with phy_modify call
drivers/net/phy/dp83867.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index adda0d0eab800..967f57ed0b65e 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -99,6 +99,7 @@
#define DP83867_PHYCR_TX_FIFO_DEPTH_MASK GENMASK(15, 14)
#define DP83867_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12)
#define DP83867_PHYCR_RESERVED_MASK BIT(11)
+#define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10)
/* RGMIIDCTL bits */
#define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf
@@ -635,7 +636,12 @@ static int dp83867_phy_reset(struct phy_device *phydev)
usleep_range(10, 20);
- return 0;
+ /* After reset FORCE_LINK_GOOD bit is set. Although the
+ * default value should be unset. Disable FORCE_LINK_GOOD
+ * for the phy to work properly.
+ */
+ return phy_modify(phydev, MII_DP83867_PHYCTRL,
+ DP83867_PHYCR_FORCE_LINK_GOOD, 0);
}
static struct phy_driver dp83867_driver[] = {
--
2.25.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v3] net: phy: dp83867: Set FORCE_LINK_GOOD to default after reset
2020-01-15 8:01 ` [PATCH v3] " Michael Grzeschik
@ 2020-01-16 12:57 ` David Miller
2020-01-16 13:16 ` [PATCH v4] " Michael Grzeschik
0 siblings, 1 reply; 9+ messages in thread
From: David Miller @ 2020-01-16 12:57 UTC (permalink / raw)
To: m.grzeschik; +Cc: netdev, andrew, f.fainelli, hkallweit1, kernel
From: Michael Grzeschik <m.grzeschik@pengutronix.de>
Date: Wed, 15 Jan 2020 09:01:07 +0100
> According to the Datasheet this bit should be 0 (Normal operation) in
> default. With the FORCE_LINK_GOOD bit set, it is not possible to get a
> link. This patch sets FORCE_LINK_GOOD to the default value after
> resetting the phy.
>
> Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
This doesn't apply to the 'net' GIT tree, please respin.
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v4] net: phy: dp83867: Set FORCE_LINK_GOOD to default after reset
2020-01-16 12:57 ` David Miller
@ 2020-01-16 13:16 ` Michael Grzeschik
2020-01-16 23:48 ` Andrew Lunn
2020-01-17 10:37 ` David Miller
0 siblings, 2 replies; 9+ messages in thread
From: Michael Grzeschik @ 2020-01-16 13:16 UTC (permalink / raw)
To: netdev; +Cc: andrew, f.fainelli, hkallweit1, kernel
According to the Datasheet this bit should be 0 (Normal operation) in
default. With the FORCE_LINK_GOOD bit set, it is not possible to get a
link. This patch sets FORCE_LINK_GOOD to the default value after
resetting the phy.
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
---
v1 -> v2: - fixed typo in subject line
- used phy_modify instead of read/write
v2 -> v3: - returned dp83867_phy_reset with phy_modify call
v3 -> v4: - rebased to net branch
drivers/net/phy/dp83867.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index 9cd9dcee4eb2e..01cf71358359a 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -97,6 +97,7 @@
#define DP83867_PHYCR_FIFO_DEPTH_MAX 0x03
#define DP83867_PHYCR_FIFO_DEPTH_MASK GENMASK(15, 14)
#define DP83867_PHYCR_RESERVED_MASK BIT(11)
+#define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10)
/* RGMIIDCTL bits */
#define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf
@@ -599,7 +600,12 @@ static int dp83867_phy_reset(struct phy_device *phydev)
usleep_range(10, 20);
- return 0;
+ /* After reset FORCE_LINK_GOOD bit is set. Although the
+ * default value should be unset. Disable FORCE_LINK_GOOD
+ * for the phy to work properly.
+ */
+ return phy_modify(phydev, MII_DP83867_PHYCTRL,
+ DP83867_PHYCR_FORCE_LINK_GOOD, 0);
}
static struct phy_driver dp83867_driver[] = {
--
2.25.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v4] net: phy: dp83867: Set FORCE_LINK_GOOD to default after reset
2020-01-16 13:16 ` [PATCH v4] " Michael Grzeschik
@ 2020-01-16 23:48 ` Andrew Lunn
2020-01-17 10:37 ` David Miller
1 sibling, 0 replies; 9+ messages in thread
From: Andrew Lunn @ 2020-01-16 23:48 UTC (permalink / raw)
To: Michael Grzeschik; +Cc: netdev, f.fainelli, hkallweit1, kernel
On Thu, Jan 16, 2020 at 02:16:31PM +0100, Michael Grzeschik wrote:
> According to the Datasheet this bit should be 0 (Normal operation) in
> default. With the FORCE_LINK_GOOD bit set, it is not possible to get a
> link. This patch sets FORCE_LINK_GOOD to the default value after
> resetting the phy.
>
> Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH v4] net: phy: dp83867: Set FORCE_LINK_GOOD to default after reset
2020-01-16 13:16 ` [PATCH v4] " Michael Grzeschik
2020-01-16 23:48 ` Andrew Lunn
@ 2020-01-17 10:37 ` David Miller
1 sibling, 0 replies; 9+ messages in thread
From: David Miller @ 2020-01-17 10:37 UTC (permalink / raw)
To: m.grzeschik; +Cc: netdev, andrew, f.fainelli, hkallweit1, kernel
From: Michael Grzeschik <m.grzeschik@pengutronix.de>
Date: Thu, 16 Jan 2020 14:16:31 +0100
> According to the Datasheet this bit should be 0 (Normal operation) in
> default. With the FORCE_LINK_GOOD bit set, it is not possible to get a
> link. This patch sets FORCE_LINK_GOOD to the default value after
> resetting the phy.
>
> Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Applied and queued up for -stable.
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2020-01-17 10:37 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
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2020-01-14 11:24 [PATCH] net: phy: dp83867: Set FORCE_LINK_GOOD do default after reset Michael Grzeschik
2020-01-14 13:25 ` Andrew Lunn
2020-01-14 16:45 ` [PATCH v2] net: phy: dp83867: Set FORCE_LINK_GOOD to " Michael Grzeschik
2020-01-14 19:21 ` Heiner Kallweit
2020-01-15 8:01 ` [PATCH v3] " Michael Grzeschik
2020-01-16 12:57 ` David Miller
2020-01-16 13:16 ` [PATCH v4] " Michael Grzeschik
2020-01-16 23:48 ` Andrew Lunn
2020-01-17 10:37 ` David Miller
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